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6. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC

value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot

instruction of a delayed branch instruction.

7. When a BREAKPOINT is set to the cacheable area, the cache block containing the

BREAKPOINT address is filled immediately before and after user program execution.

8. Note on DSP repeat loop:

A BREAKPOINT is equal to a branch instruction. In some DSP repeat loops, branch

instructions cannot be set. For these cases, do not set BREAKPOINTs. Refer to the hardware

manual for details.

9. If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area, a

mark ! will be displayed in the [BP] area of the address on the [Source] or [Disassembly]

window by refreshing the [Memory] window, etc. after Go execution. However, no break will

occur at this address. When the program halts with the break condition, the mark ! disappears.

6.5.6 Notes on Setting the [Break Condition] Dialog Box and the BREAKCONDITION_

SET Command

1. When [Go to cursor], [Step In], [Step Over], or [Step Out] is selected, the settings of Break

Condition 2 are disabled.

2. Break Condition 2 is disabled when an instruction to which a BREAKPOINT has been set is

executed. Accordingly, do not set a BREAKPOINT to an instruction which satisfies Break

Condition 2.

3. When a Break Condition is satisfied, emulation may stop after two or more instructions have

been executed.

4. If a PC break address condition is set to the slot instruction after a delayed branch instruction,

user program execution cannot be terminated before the slot instruction execution; execution

stops before the branch destination instruction.

5. Break Condition 1,2 is used as the measurement range in the performance measurement

function when (P) is added and displayed as Enable(P) on the [Condition] page. This applies

when the Break Condition is displayed with the BREAKCONDITION_DISPLAY command

in the command-line function. In this case, a break does not occur when Break Condition 1,2

is satisfied.

6. A break will not occur with the execution counts specified on the execution of the multi-step

instruction.

6.5.7 Notes on Setting the [Trace] Window

When a completion-type exception occurs during exception branch acquisition, the next address to

the address in which an exception occurs is acquired.

6.5.8 Notes on Setting the UBC_MODE Command

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