
20
CK
V
OH
V
OL
A17 to A0
_CSn
T1
t
AD
t
CSD1
t
CSD2
t
RSD1
t
OE
t
RSD2
t
ACC
t
RDS
t
RDH
t
WSD1
t
WSD2
t
WR
t
WDH
t
WDD
t
AS
Tw T2
_RD
(When read)
_WRx
(When written)
Note: tRDH: Specified from the earliest negation timing from A17 to A0, _CSn, or _RD.
D7 to D0
(When read)
D7 to D0
(When written)
Figure 3.2 Basic Bus Cycle (Software Wait)
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