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5.5.3 On-Emulator Break
• A break will occur several cycles after a condition is satisfied.
• The address bus and data bus conditions are satisfied on the bus cycles where the values on the address bus
or data bus match. Consider the following points when setting these conditions.
⎯ 32-bit bus area
• Longword access
Longword data is read and written in a single bus cycle. A data condition is only valid for a longword
access when specified as longword. An address condition is only valid for a longword access when
specified as a multiple of four.
• Word access
Word data is read and written in a single bus cycle. A data condition is only valid for a word access
when specified as word. An address condition is only valid for a word access when specified as a
multiple of two.
• Byte access
Byte data is read and written in a single bus cycle. A data condition is only valid for a byte access
when specified as byte. Any address condition, whether an even or odd address, is valid.
⎯ 16-bit bus area
• Longword access
Longword data is read and written in two bus cycles. A data condition is only valid for a longword
access when specified as word. An address condition is only valid for a longword access when
specified as a multiple of two.
• Word access
Word data is read and written in a single bus cycle. A data condition is only valid for a word access
when specified as word. Any multiple of two is a valid address condition.
• Byte access
Byte data is read and written in a single bus cycle. A data condition is only valid for a byte access
when specified as byte. Any address condition, whether an even or odd address, is valid.
⎯ 8-bit bus area
All accesses are done in bytes in this area (a longword is accessed in four byte cycles, and a word in two
byte cycles). Any address condition, whether an even or odd address, is valid. A data condition is only
valid when specified as byte.
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