Renesas Renasas Single-Chip Microcomputer SH7086 Bedienungsanleitung

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology C

Quick Reference-2MOVDir MOVHH MOVHL MOVLH MOVLLMULMULUNEGNOPNOTORPOPPOPCPOPMPUSHPUSHAPUSHCPUSHMREITRMPAROLCRORC 96 97 98 9910010110310

82Chapter 3 Functions3.2 Functions[ Operation ]When jump distance specifier (.length) is (.W) When jump distance specifier (.length) is (.A)PC

83Chapter 3 Functions3.2 FunctionsJuMP Special pageJump to special page[ Syntax ]JMPS srcJMPS JMPS[ Operation ]PCH 0F16PCML M( FFFFE16 – src

84Chapter 3 Functions3.2 FunctionsJump SubRoutineSubroutine call[ Syntax ]JSR(.length) label[ Flag Change ][ Description Example ][ Related Instruc

85Chapter 3 Functions3.2 FunctionsUIOBSZDCIndirect subroutine call[ Related Instructions ] JSR,JSRSW , AJump SubRoutine IndirectJSRI190[ Instructio

86Chapter 3 Functions3.2 FunctionsJump SubRoutine Special pageSpecial page subroutine callJSRS JSRS[ Syntax ]JSRS src[ Function ]• This instruction

87Chapter 3 Functions3.2 FunctionsLoaD Control registerTransfer to control register[ Flag Change ][ Description Example ][ Related Instructions ] P

88Chapter 3 Functions3.2 FunctionsRegister information for the task whose task number = 0. (See the above diagram.)SP correction value for the tas

89Chapter 3 Functions3.2 FunctionsLoaD from EXtra far data areaTransfer from extended data area[ Flag Change ][ Description Example ][ Related Inst

90Chapter 3 Functions3.2 FunctionsLoaD INTB registerTransfer to INTB register[ Flag Change ][ Description Example ][ Related Instructions ] LDC,STC

91Chapter 3 Functions3.2 FunctionsLoaD Interrupt Permission LevelSet interrupt enable level[ Syntax ]LDIPL src[ Flag Change ][ Description Example

Quick Reference-3MOV TransferMOVA Transfer effective addressMOVDir Transfer 4-bit dataPOP Restore register/memoryPOPM Restore multiple registersPUSH S

923.2 FunctionsChapter 3 FunctionsMOVeTransfer[ Related Instructions ] LDE,STE,XCHG[ Description Example ][ Selectable src/dest ][ Function ]MOV MOV

933.2 FunctionsChapter 3 Functions[src/dest Classified by Format]G formatsrc destR0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3A0/A0*1A1/A1

943.2 FunctionsChapter 3 FunctionsMOVe effective AddressTransfer effective address[ Flag Change ][ Description Example ][ Related Instructions ] PUS

953.2 FunctionsChapter 3 FunctionsMOVe nibbleTransfer 4-bit dataMOVDirMOVDir[ Operation ][ Syntax ]MOVDirsrc,dest[ Description Example ]DirOperation

963.2 FunctionsChapter 3 FunctionsMULtipleSigned multiply[ Syntax ]MUL.size src,dest[ Description Example ][ Related Instructions ] DIV,DIVU,DIVX,MU

973.2 FunctionsChapter 3 Functionssrc destR0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3A0/A0*1A1/A1*1[A0] [A1] A0/A0*1A1/A1 [A0] [A1]dsp:8

983.2 FunctionsChapter 3 FunctionsNEGateTwo’s complement[ Syntax ]NEG.size dest[ Flag Change ][ Description Example ][ Related Instructions ] NOT[ F

993.2 FunctionsChapter 3 Functions No OPerationNo operation[ Flag Change ][ Description Example ]NOP[ Function ]NOP NOP[ Syntax ]NOP• This instructi

1003.2 FunctionsChapter 3 FunctionsNOTInvert all bits[ Related Instructions ] NEGNOT NOT[ Operation ]________dest dest[ Function ]• This in

101Chapter 3 Functions3.2 Functions[ Instruction Code/Number of Cycles ]Page=ORLogically OR[ Description Example ]OR.B Ram:8[SB],R0LOR.B:G A0,R0L ;

Quick Reference-4116DADD Decimal add without carryDEC DecrementDIV Signed divideDIVU Unsigned divideDIVX Singed divideDSBB Decimal subtract with borro

102Chapter 3 Functions3.2 Functions[src/dest Classified by Format]G formatsrc destR0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3A0/A0*1A1

103Chapter 3 Functions3.2 FunctionsPOPRestore register/memory[ Flag Change ]POP.B R0LPOP.W A0[ Related Instructions ] PUSH,POPM,PUSHM[ Selectable d

104Chapter 3 Functions3.2 FunctionsPOP Control registerRestore control register[ Flag Change ][ Description Example ][ Related Instructions ] PUSH

105Chapter 3 Functions3.2 FunctionsPOP MultipleRestore multiple registers[ Description Example ][ Related Instructions ] POP,PUSH,PUSHM[ Selectable

106Chapter 3 Functions3.2 FunctionsPUSHSave register/memory/immediate data[ Flag Change ][ Description Example ][ Related Instructions ] POP,POPM,

107Chapter 3 Functions3.2 FunctionsPUSH effective AddressSave effective address [ Flag Change ][ Description Example ][ Related Instructions ] MOV

108Chapter 3 Functions3.2 FunctionsPUSH Control registerSave control register[ Syntax ]PUSHC src[ Flag Change ][ Description Example ]PUSHC SB[ Re

109Chapter 3 Functions3.2 FunctionsPUSH MultipleSave multiple registers[ Syntax ]PUSHM src[ Description Example ][ Related Instructions ] POP,PUSH,

110Chapter 3 Functions3.2 FunctionsREturn from InTerruptReturn from interrupt[ Syntax ]REIT[ Flag Change ][ Description Example ][ Function ]REIT

1113.2 FunctionsChapter 3 FunctionsRepeat MultiPle & AdditionCalculate sum-of-products[ Description Example ]RMPA RMPA[ Syntax ]RMPA.sizeB , W

Quick Reference-5Other132133LDCTX Restore contextLDINTB Transfer to INTB registerLDIPL Set interrupt enable levelNOP No operationPOPC Restore control

1123.2 FunctionsChapter 3 FunctionsROtate to Left with CarryRotate left with carryC[ Description Example ][ Related Instructions ] RORC,ROT,SHA,SH

1133.2 FunctionsChapter 3 FunctionsROtate to Right with CarryRotate right with carry[ Syntax ]RORC.size dest[ Flag Change ][ Related Instructions

1143.2 FunctionsChapter 3 FunctionsROTateRotate[ Related Instructions ] ROLC,RORC,SHA,SHLROT ROT[ Syntax ]ROT.size src,destB , W• This instruction

1153.2 FunctionsChapter 3 FunctionsReTurn from SubroutineReturn from subroutine[ Flag Change ][ Description Example ]RTSRTS RTS[ Syntax ]RTS[ Oper

1163.2 FunctionsChapter 3 FunctionsSuBtract with BorrowSubtract with borrow[ Syntax ]SBB.size src,dest[ Operation ]___dest dest – s

1173.2 FunctionsChapter 3 FunctionsSuBtract then Jump on Not ZeroSubtract & conditional jump[ Selectable src/dest/label ][ Related Instruction

1183.2 FunctionsChapter 3 FunctionsSHift ArithmeticShift arithmetic[ Syntax ]SHA.size src,dest[ Related Instructions ] ROLC,RORC,ROT,SHLSHAB , W ,

1193.2 FunctionsChapter 3 FunctionsSHift LogicalShift logical[ Syntax ]SHL.size src,dest[ Related Instructions ] ROLC,RORC,ROT,SHASHL SHLB , W , L

1203.2 FunctionsChapter 3 FunctionsString MOVe Backward Transfer string backward[ Syntax ]SMOVB.size[ Description Example ]SMOVB.B[ Related Instru

1213.2 FunctionsChapter 3 FunctionsString MOVe ForwardTransfer string forward[ Syntax ]SMOVF.size[ Description Example ][ Related Instructions ] S

Quick Reference-6R0L/R0R0H/R1R1L/R2R1H/R3An[An]dsp:8[An]dsp:8[SB/FB]dsp:16[An]dsp:16[SB]abs16#IMM8#IMM16#IMM20#IMMSee pagefor functionSee page forinst

122Chapter 3 Functions3.2 FunctionsString SToReStore string[ Function ][ Flag Change ][ Description Example ]SSTR.B[ Related Instructions ] SMOVB,

123Chapter 3 Functions3.2 FunctionsTransfer from control registerSTore from Control register[ Syntax ]STC src,dest[ Description Example ][ Related

124Chapter 3 Functions3.2 FunctionsSTore ConTeXtSave contextSTCTX Ram,Rom_TBL[ Related Instructions ] LDCTX[ Flag Change ]STCTX STCTX[ Syntax ]STC

125Chapter 3 Functions3.2 FunctionsSTore to EXtra far data areaTransfer to extended data area[ Flag Change ][ Description Example ]STE.B R0L,[A1A0

126Chapter 3 Functions3.2 FunctionsSTore on Not ZeroConditional transfer[ Function ][ Flag Change ][ Description Example ][ Related Instructions ]

127Chapter 3 Functions3.2 FunctionsSTore on ZeroConditional transfer[ Syntax ]STZ src,dest[ Function ][ Flag Change ]• This instruction transfers

128Chapter 3 Functions3.2 Functions[ Instruction Code/Number of Cycles ]Page=STore on Zero eXtentionConditional transfer[ Syntax ]STZX src1,src2,d

129Chapter 3 Functions3.2 Functions[ Selectable src/dest ]SUBtractSubtract without borrow[ Syntax ]SUB.size (:format) src,dest[ Operation ]dest

130Chapter 3 Functions3.2 Functions[src/dest Classified by Format]G formatsrc destR0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3A0/A0*1A1

131Chapter 3 Functions3.2 FunctionsTeSTTest[ Syntax ]TST.size src,dest[ Description Example ]TST.B #3,R0LTST.B A0,R0L ; A0's 8 low-order bits

Quick Reference-7LDINTBLDIPLMOV*1MOVAMOVDirMULMULUNEGNOTORPOPPOPM*1PUSHPUSHAPUSHM*1ROLCRORCROTSBBSBJNZ*1SHA*1SHL*1STC*1STCTX*1STE*1R0L/R0R0H/R1R1L/R2R

132Chapter 3 Functions3.2 FunctionsUNDefined instructionInterrupt for undefined instruction[ Syntax ]UND[ Flag Change ][ Description Example ]UND

133Chapter 3 Functions3.2 FunctionsWAITWait[ Syntax ]WAIT[ Flag Change ][ Description Example ][ Function ]WAIT WAIT• This instruction halts progr

134Chapter 3 Functions3.2 FunctionseXCHanGeExchange[ Flag Change ][ Description Example ][ Function ][ Selectable src/dest ]XCHG XCHG[ Syntax ]XCH

135Chapter 3 Functions3.2 FunctionseXclusive ORExclusive OR[ Syntax ]XOR.size src,dest[ Flag Change ][ Selectable src/dest ][ Description Example

136Chapter 3 Functions3.2 Functions

Chapter 4Instruction Code/Number of Cycles4.1 Guide to This Chapter4.2 Instruction Code/Number of Cycles

138Chapter 4 Instruction Code4.1 Guide to This Chapter4.1 Guide to This ChapterThis chapter describes instruction code and number of cycles for ea

139Chapter 4 Instruction Code4.1 Guide to This Chapter(1) MnemonicShows the mnemonic explained in this page.(2) SyntaxShows an instruction syntax

140Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesABS(1) ABS.size destdest codedsp8)dsp16/abs16.size.B.WSIZE01dsp

141Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cyclesdsp8dest codedsp16/abs16)src codedsp8)dsp16/abs16SRC/DESTsrc/de

Quick Reference-8R0L/R0R0H/R1R1L/R2R1H/R3An[An]dsp:8[An]dsp:8[SB/FB]dsp:16[An]dsp:16[SB]abs16#IMM8#IMM16#IMM20#IMMSTNZSTZSTZXSUBTSTXCHGXOR134135126127

142Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesADCF(1) ADCF.size destdest codedsp8)dsp16/abs16.size.B.WSIZE01d

143Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesADD(2) ADD.size:Q #IMM, destdest codedsp8)dsp16/abs16.size.B.WS

144Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesADDRndsp:8[SB/FB]011100101110111R0HR0Ldsp:8[SB]dsp:8[FB]abs16ab

145Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesADD(4) ADD.size:G src, dest1010000SIZESRC DESTdsp8dest codedsp1

146Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles3/2[ Number of Bytes/Number of Cycles ]ADD#IMM8#IMM16.size.B.WS

147Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesADD(7) ADD.size:Q #IMM, SP[ Number of Bytes/Number of Cycles ]2

148Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesADJNZ1111100SIZEIMM4 DEST(1) ADJNZ.size #IMM, dest, labeldest c

149Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesAND0111011SIZE0 0 1 0 DEST(1) AND.size:G #IMM, destdest codedsp

150Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(AND(3) AND.size:G src, dest1001000SIZESRC DESTdsp8dsp16/abs16)

151Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(4) AND.B:S src, R0L/R0Hsrc codedsp8)abs16dsp:8[SB/FB]2/3Rn1/2a

Quick Reference-9ADD*1ADJNZ*1JCndJMPJMPI*1JSRJSRI*1LDC*1LDCTXLDE*1MOV*1POPCPOPM*1PUSHCPUSHM*1SBJNZ*1SHA*1SHL*1STC*1STCTX*1STE*1dsp:20[A0]dsp:20[A1]abs

152Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesBAND011111100100 SRC(1) BAND srcsrc codedsp8dsp16)[ Number of B

153Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(2) BCLR:S bit, base:11[SB]BCLRdsp8dest code[ Number of Bytes/N

154Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesBMCnddest4/7bit,base:8[SB/FB]4/104/64/6bit,Rn bit,An [An]bit,ba

155Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesBMCnd011111011101 CND2/1BNAND(1) BNAND srcsrc codedsp8dsp16[ Nu

156Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesBNOR011111100111 SRC(1) BNOR srcsrc codedsp8dsp16)[ Number of B

157Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesBNOT(2) BNOT:S bit, base:11[SB]dest codedsp8[ Number of Bytes/N

158Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(1) BNXOR srcsrc codedsp8dsp16)[ Number of Bytes/Number of Cycl

159Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesBRK(1) BRK00000000[ Number of Bytes/Number of Cycles ]1/27(1) B

160Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(2) BSET:S bit, base:11[SB]dsp8dest code0 1 0 0 1 BIT[ Number o

161Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cyclesdest codedsp8dsp16)BTST(2) BTST:S bit, base:11[SB]0 1 0 1 1 BIT

Quick Reference-10BANDBCLRBMCndBNANDBNORBNOTBNTSTBNXORBORBSETBTSTBTSTCBTSTSBXORFCLRFSETbit,Rnbit,An[An]base:8[An]bit,base:8[SB/FB]base:16[An]bit,base:

162Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesBTSTS0 1 1 1 1 1 1 0 0 0 0 1 DEST(1) BTSTS destdest codedsp8dsp

163Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesCMP0111011SIZE1 0 0 0 DEST(1) CMP.size:G #IMM, destdest codedsp

164Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesCMP(2) CMP.size:Q #IMM, destdest codedsp8)dsp16/abs16 0+1+2+3+

165Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesCMP[ Number of Bytes/Number of Cycles ]dsp:8[SB/FB]3/3Rn2/1abs1

166Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesCMP1100000SIZESRC DEST(4) CMP.size:G src, destdsp8dest codedsp1

167Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(5) CMP.B:S src, R0L/R0HCMPsrc codedsp8)abs16DADC01111100111011

168Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDADC(2) DADC.W #IMM16, R0[ Number of Bytes/Number of Cycles ]4/

169Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDADC(4) DADC.W R1, R0[ Number of Bytes/Number of Cycles ]2/5DAD

170Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDADD(2) DADD.W #IMM16, R0#IMM16[ Number of Bytes/Number of Cycl

171Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDADD(4) DADD.W R1, R0[ Number of Bytes/Number of Cycles ]2/5DEC

Chapter 1Overview1.1 Features of M16C/60, M16C/20, M16C/Tiny series1.2 Address Space1.3 Register Configuration1.4 Flag Register (FLG)1.5 Register

172Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDEC(2) DEC.W dest[ Number of Bytes/Number of Cycles ]1/1DIV(1)

173Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDIV(2) DIV.size srcdsp8src codedsp16/abs16)srcdsp:8[A0]dsp:8[A1

174Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDIVU0111011SIZE1 1 0 0 SRC(2) DIVU.size srcdsp8src codedsp16/ab

175Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDIVX(2) DIVX.size srcdsp8src codedsp16/abs16)srcdsp:8[A0]dsp:8[

176Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDSBB(2) DSBB.W #IMM16, R0#IMM16[ Number of Bytes/Number of Cycl

177Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDSBB(4) DSBB.W R1, R0[ Number of Bytes/Number of Cycles ]2/4DSU

178Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDSUB(2) DSUB.W #IMM16, R0#IMM16[ Number of Bytes/Number of Cycl

179Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesDSUB(4) DSUB.W R1, R0[ Number of Bytes/Number of Cycles ]2/4(1)

180Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesEXITD(1) EXITD[ Number of Bytes/Number of Cycles ]2/9EXTS(1) EX

181Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesEXTS(2) EXTS.W R0[ Number of Bytes/Number of Cycles ]2/3[ Numbe

Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to chang

2Chapter 1 Overview1.1 Features of M16C/60, M16C/20, M16C/Tiny seriesThe M16C/60, M16C/20, M16C/Tiny series are single-chip microcomputer developed f

182Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesFSET(1) FSET dest[ Number of Bytes/Number of Cycles ]2/2INC(1)

183Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesINC(2) INC.W destINT(1) INT #IMM11[ Number of Bytes/Number of C

184Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesINTO(1) INTO[ Number of Bytes/Number of Cycles ]1/1JCnd(1) JCnd

185Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesJCnd(2) JCndlabeldsp8label code3/2[ Number of Bytes/Number of C

186Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesJMP(2) JMP.B labellabel code[ Number of Bytes/Number of Cycles

187Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles[ Number of Bytes/Number of Cycles ]4/4(1) JMPI.W srcsrcdsp:8[A

188Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesJMPI(2) JMPI.A srcJMPS(1) JMPS #IMM8#IMM8[ Number of Bytes/Numb

189Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesJSR(1) JSR.W labeldsp16 = address indicated by label – (start a

190Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(1) JSRI.W src(2) JSRI.A srcsrcdsp:8[A0]dsp:8[A1]dsp:8[SB]dsp:8

191Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesJSRS(1) JSRS #IMM8#IMM8[ Number of Bytes/Number of Cycles ]2/13

3Chapter 1 OverviewThe SFR area in eachmodel extends towardlower-address locationsas much as available.The RAM area in eachmodel extends towardhigher-

192Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesLDC(2) LDC src, destdsp8src codedsp16/abs16)[ Number of Bytes/N

193Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesLDE(1) LDE.size abs20, destdestdsp:8[A0]dsp:8[A1]dsp:8[SB]dsp:8

194Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesLDE(3) LDE.size [A1A0], destdest codedsp8)dsp16/abs16destdsp:8[

195Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(1) LDIPL #IMM[ Number of Bytes/Number of Cycles ]2/2(1) MOV.si

196Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesMOV1101100SIZEIMM4 DEST(2) MOV.size:Q #IMM, destdest codedsp8)d

197Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesMOVdsp:8[SB/FB]3/2Rn2/1abs164/2dest[ Number of Bytes/Number of

198Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesMOV(4) MOV.size:S #IMM, dest#IMM8#IMM16.size.B.WSIZE10DESTdestA

199Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(MOV(6) MOV.size:G src, destdsp8dest codedsp16/abs16)src codeds

200Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesMOV(7) MOV.B:S src, destsrc codedsp8)abs16DESTdestA0A101MOV(8)

201Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesMOV(9) MOV.B:S src, R0L/R0Hsrc codedsp8)abs16MOV(10) MOV.size:G

4Chapter 1 Overview1.3 Register Configuration1.3 Register ConfigurationThe central processing unit (CPU) contains the 13 registers shown in Figure 1

202Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesMOVMOVA(11) MOV.size:G src, dsp:8[SP]dest codedsp8)dsp8src code

203Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesMOVDir(1) MOVDirR0L, destdest codedsp8)dsp16/abs16b7 b0 b7 b00

204Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesMOVDir(2) MOVDirsrc, R0Ldest codedsp8)dsp16/abs16b7 b0 b7 b0011

205Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesMUL(1) MUL.size #IMM, destdest codedsp8dsp16/abs16)#IMM8#IMM16D

206Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(MUL(2) MUL.size src, destdsp8dest codedsp16/abs16)src codedsp8

207Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesMULU(1) MULU.size #IMM, dest.size.B.WSIZE01DESTdestdsp:8[A0]dsp

208Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(MULU(2) MULU.size src, destdsp8dest codedsp16/abs16)src codeds

209Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesNEG(1) NEG.size destdest codedsp8)dsp16/abs16destdsp:8[A0]dsp:8

210Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(2) NOT.B:S destNOTdest codedsp8)abs16NOT(1) NOT.size:G destdes

211Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesOR(1) OR.size:G #IMM, destdest codedsp8)dsp16/abs16#IMM8#IMM16d

5Chapter 1 Overview1.3.2 Address registers (A0 and A1)The address registers (A0 and A1) consist of 16 bits, and have the similar functions as the dat

212Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(OR(3) OR.size:G src, destdsp8dest codedsp16/abs16)src codedsp8

213Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesOR(4) OR.B:S src, R0L/R0Hdest codedsp8)abs16POP(1) POP.size:G d

214Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(2) POP.B:S dest1/3POP(3) POP.W:S dest1/3[ Number of Bytes/Numb

215Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesPOPC(1) POPC destPOPM(1) POPM destDESTdest DEST000001010011---I

216Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesPUSH(1) PUSH.size:G #IMM#IMM8#IMM16.size.B.WSIZE013/2(2) PUSH.s

217Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesPUSH(3) PUSH.B:S src1/2[ Number of Bytes/Number of Cycles ]PUSH

218Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesPUSHA(1 ) PUSHA srcdsp8src codedsp16/abs16)[ Number of Bytes/Nu

219Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesPUSHM[ Number of Bytes/Number of Cycles ](1) PUSHM srcSRC2/2

220Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles*1 m denotes the number of operation performed.*2 If the size s

221Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesRORC(1) RORC.size destdest codedsp8)dsp16/abs16destdsp:8[A0]dsp

6Chapter 1 Overview1.4 Flag Register (FLG)Figure 1.4.1 shows a configuration of the flag register (FLG). The function of each flag is detailed below

222Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesROT(1) ROT.size #IMM, destdest codedsp8)dsp16/abs16100010011010

223Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesROT(2) ROT.size R1H, destdest codedsp8)dsp16/abs16DESTdestdsp:8

224Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSBB(1) SBB.size #IMM, destdest codedsp8)dsp16/abs16#IMM8#IMM16d

225Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(SBB(2) SBB.size src, destdsp8dest codedsp16/abs16)src codedsp8

226Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSBJNZ(1) SBJNZ.size #IMM, dest, label1111100SIZEIMM4 DESTlabel

227Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSHA(1) SHA.size #IMM, dest1111000SIZEIMM4 DESTdest codedsp8)dsp

228Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSHA0111010SIZE1 1 1 1 DEST(2) SHA.size R1H, destdest codedsp8)d

229Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSHA(4) SHA.L R1H, dest2/4+m[ Number of Bytes/Number of Cycles ]

230Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSHL(1) SHL.size #IMM, destdest codedsp8)dsp16/abs16100010011010

231Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSHL(2) SHL.size R1H, destdest codedsp8)dsp16/abs16DESTdestdsp:8

7Chapter 1 Overview1.4 Flag Register (FLG)Figure 1.4.1 Configuration of flag register (FLG)IPL U I O B S Z D Cb15 b0Carry flagDebug flagZero flagSig

232Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSHL(4) SHL.L R1H, dest2/4+m[ Number of Bytes/Number of Cycles ]

233Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles0111110SIZE11101000SMOVF.size.B.WSIZE012/5+5 m[ Number of By

234Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSTC0 1 1 1 1 0 1 1 1 SRC DEST(1) STC src, destdest Codedsp8)dsp

235Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSTCTXabs16[ Number of Bytes/Number of Cycles ]7/11+2 mSTE(1)

236Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(2) STE.size src, dsp:20[A0]STEdsp8src codedsp16/abs16)srcdsp:8

237Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSTNZ(1) STNZ #IMM8, destdsp:8[SB/FB]3/2Rn2/1abs164/2destBytes/C

238Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSTZX(1) STZX #IMM81, #IMM82, dest1 1 0 1 1 DEST[ Number of Byte

239Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSUB(2) SUB.B:S #IMM8, destdsp:8[SB/FB]3/3Rn2/1abs164/3destRndsp

240Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(SUB(3) SUB.size:G src, destdsp8dest codedsp16/abs16)src codeds

241Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesSUB(4) SUB.B:S src, R0L/R0Hdest codedsp8)abs16dsp:8[SB/FB]2/3Rn

8Chapter 1 Overview1.5 Register BankR0 H Lb15 b8b7 b0R3A0A1FBR1 H LR2R0 H Lb15 b8b7 b0R3A0A1FBR1 H LR2Register bank 0 (B flag = 0) Register bank 1 (

242Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesTST(2) TST.size src, destdsp8dest codedsp16/abs16)src codedsp8)

243Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of Cycles(1) UNDUND[ Number of Bytes/Number of Cycles ]1/20Bytes/Cycles(

244Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesXCHG(1) XCHG.size src, destdest codedsp8)dsp16/abs16.size.B.WSI

245Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesXOR(1) XOR.size #IMM, destdest codedsp8)dsp16/abs16#IMM8#IMM16d

246Chapter 4 Instruction Code/Number of Cycles4.2 Instruction Code/Number of CyclesXOR(2) XOR.size src, dest1000100SIZESRC DESTdsp8dest codedsp16/

Chapter 5Interrupt5.1 Outline of Interrupt5.2 Interrupt Control5.3 Interrupt Sequence5.4 Return from Interrupt Routine5.5 Interrupt Priority5.6

248Chapter 5 InterruptUndefined instruction (UND instruc-tion)Overflow (INTO instruction)BRK instructionINT instructionRemarksInterrupt generated by

249Chapter 5 Interrupt5.1.2 Software InterruptsSoftware interrupts are generated by some instruction that generates an interrupt request when ex-ec

250Chapter 5 Interrupt5.1.3 Hardware InterruptsThere are Two types in hardware Interrupts; special interrupts and Peripherai I/O interrupts.(1) Sp

251Chapter 5 InterruptFSET ITime5.2 Interrupt ControlThe following explains how to enable/disable maskable interrupts and set acknowledge priority.

9Chapter 1 Overview1.6 Internal State after Reset is Cleared1.6 Internal State after Reset is ClearedThe following lists the content of each registe

252Chapter 5 InterruptWhen the processor interrupt priority level (IPL) or the interrupt priority level of some interrupt ischanged, the altered lev

253Chapter 5 Interrupt5.2 Interrupt ControlExample 1:Using the NOP instruction to keep the program waiting until the interrupt control register is

254Chapter 5 Interrupt5.3 Interrupt SequenceAn interrupt sequence — what are performed over a period from the instant an interrupt is accepted to t

255Chapter 5 Interrupt5.3.1 Interrupt Response TimeThe interrupt response time means a period of time from when an interrupt request is generated t

256Chapter 5 InterruptValue that is set to IPL70Not changed5.3.2 Changes of IPL When Interrupt Request AcknowledgedWhen an interrupt request is ack

257Chapter 5 InterruptThe register save operation performed in an interrupt sequence differs depending on whether the con-tent of the stack pointer

258Chapter 5 Interrupt5.4 Return from Interrupt RoutineAs you execute the REIT instruction at the end of the interrupt routine, the contents of the

259Chapter 5 Interrupt5.5 Interrupt PriorityIf two or more interrupt requests are sampled active at the same time, whichever interrupt request is a

260Chapter 5 Interrupt5.6 Multiple InterruptsThe following shows the internal bit states when control has branched to an interrupt routine:• The i

261Chapter 5 InterruptI = 0IPL = 0I = 1I = 0IPL = 3I = 1I = 0IPL = 5REITI = 1IPL = 3REITI = 1IPL = 0I = 0IPL = 2REITI = 1IPL = 0Interrupt priority l

10Chapter 1 Overview1.7 Data Typesb7 b0b7 b0 Sb15 b0 SSigned byte (8 bit) integerUnsigned byte (8 bit) integerSigned word (16 bit) integerUnsigned wo

262Chapter 5 Interrupt5.7 Precautions for Interrupts5.7.1 Reading address 0000016Do not read the address 0000016 in a program. When a maskable inter

263Chapter 5 InterruptExample 1:Using the NOP instruction to keep the program waiting until the interrupt control register is modifiedINT_SWITCH1:FC

264Chapter 5 Interrupt

Chapter 6Calculation Number of Cycles6.1 Instruction queue buffer

62666.1 Instruction queue bufferCalculation number of cycles6.1 Instruction queue bufferThe M16C/60, M16C/20, M16C/Tiny series have 4-stage (4-byte) i

6267Calculation number of cycles6.1 Instruction queue bufferSample programAddress Code InstructionFC050 64 JMP TEST_11FC051 04 NOP FC052 04 NOPFC053 0

62686.1 Instruction queue bufferCalculation number of cyclesSample programAddress Code InstructionFC058 64 JMP TEST_11FC059 04 NOPFC05A 04 NOP FC05B

6269Calculation number of cycles6.1 Instruction queue bufferSample programAddress Code InstructionFC06C 64 JMP TEST_11FC06D 04 NOPFC06E 04 NOP FC06F

62706.1 Instruction queue bufferCalculation number of cyclesSample programAddress Code InstructionFC058 64 JMP TEST_11FC059 04 NOPFC05A 04 NOP FC05B

Q&A-1 Q & AInformation in a Q&A form to be used to make the most of the M16C family is given below.Usually, one question and the answer to

11Chapter 1 Overview1.7 Data Types1.7.2 DecimalThis type of data can be used in DADC, DADD, DSBB, and DSUB.Pack format(2 digits)Pack format(4 digits

Q&A-2CPUQASB and FB function in the same manner, so you can use them as intended in programming in theassembly language. If you write a program in

Q&A-3InterruptQAYes. But there can be a chance that the microcomputer runs away out of control if an interruptrequest occurs in changing the value

Q&A-4CPUQAWhat is the difference between the user stack pointer (USP) and the interrupt stack pointer (ISP)?,What are their roles?You use USP when

Q&A-5CPUQAHow does the instruction code become if I use a bit instruction in absolute addressing ?An explanation is given here by taking BSET bit,

Q&A-6CPUQAWhat is the difference between the DIV instruction and the DIVX instruction?Either of the DIV instruction and the DIVX instruction is an

Glossary-1GlossaryTechnical terms used in this software manual are explained below. They are good in this manual only.

Glossary-2borrow Tomove a digit to the next lower position. carrycarry Tomove a digit to the next higher position. borrowcontext Registers that a pro

Glossary-3Term Meaning Related wordmacro instructionMSBoperandoperationoperation codeoverflowpackSFR areaAn instruction, written in a source language,

Glossary-4Term Meaning Related wordshift outsign bitsign extensionstack framestringunpackzero extensionTo move the content of a register either to the

Symbol-1Table of symbolsSymbols used in this software manual are explained below. They are good in this manual only.

M16C/60, M16C/20, M16C/Tiny SeriesSoftware Manual16Rev. 4.00 2004.01RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTERAll information contained in these mater

12Chapter 1 Overview1.7 Data Types1.7.3 Bits● Register bitsFigure 1.7.3 shows register bit specification.Register bits can be specified by register

Symbol-2Symbol MeaningTransposition from the right side to the left sideInterchange between the right side and the left sideAdditionSubtractionMultipl

Index-1IndexAA0 and A1 ••• 5A1A0 ••• 5Address register ••• 5Address space ••• 3Addressing mode ••• 22BB flag ••• 6Byte (8-bit) data ••• 16CC flag •••

Index-2Operation ••• 37Overflow flag ••• 6PPC ••• 5Processor interrupt priority level ••• 7Program counter ••• 5RR0, R1, R2, and R3 ••• 4R0H, R1H •••

REVISION HISTORYRev. Date DescriptionPage SummaryM16C/60, M16C/20, M16C/Tiny Series Software ManualB Sep 09, 1999Page 104 [Operation] Line 3Add to “ *

REVISION HISTORYRev. Date DescriptionPage SummaryM16C/60, M16C/20, M16C/Tiny Series Software ManualB3 Jul 09, 2002 –Page 127 [ Function ]• This instr

REVISION HISTORYRev. Date DescriptionPage SummaryM16C/60, M16C/20, M16C/Tiny Series Software ManualB3 Jul 09, 2002 –Page 132 [ Function ] perform op

REVISION HISTORYRev. Date DescriptionPage SummaryM16C/60, M16C/20, M16C/Tiny Series Software Manual4.00 Jan 21, 2004 253, 262Add TECHNICAL NEWS NO M16

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTERSOFTWARE MANUALM16C/60, M16C/20, M16C/Tiny SeriesPublication Data : Rev.B3 Jul 15, 2002Rev.4.00 Jan 21, 2004Pu

1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 JapanM16C/60, M16C/20, M16C/Tiny SeriesREJ09B0137-0400ZSoftware Manual

13Chapter 1 Overview0n-1nn+1nÅ{1 n nÅ|1 0b7 b0b7 b0b7 b0 b7 b0b7 b0BSET 2,AH ;b7 b2 b0b15 b10 b8b7 b0b87 b82 b80b79 b72 b7 b0b23 b18 b16b15 b8b7 b0BSE

14Chapter 1 Overview1.7 Data Types(2) SB/FB relative bit specificationFor SB/FB-based relative addressing, use bit 0 of the address that is the sum

15Chapter 1 Overview1.7 Data Types1.7.4 StringString is a type of data that consists of a given length of consecutive byte (8-bit) or word (16-bit)

16Chapter 1 Overview1.8 Data Arrangement1.8 Data Arrangement1.8.1 Data Arrangement in RegisterFigure 1.8.1 shows the relationship between a registe

17Chapter 1 Overviewb7 b0N DATA(L)N+1 DATA(H)N+2N+3b7 b0N DATAN+1N+2N+3MOV.B N,R0HMOV.W N,R0R0HLb15 b0R0HLb15 b0DATADATA(H) DATA(L)Word (16-bit) dataB

18Chapter 1 Overview1.9 Instruction Format1.9 Instruction FormatThe instruction format can be classified into four types: generic, quick, short, and

19Chapter 1 Overview255254181.10 Vector Table1.10 Vector TableThe vector table comes in two types: a special page vector table and an interrupt vect

20Chapter 1 Overview1.10 Vector Table1.10.2 Variable Vector TableThe variable vector table is an address-variable vector table. Specifically, this

Chapter 2Addressing Modes2.1 Addressing Modes2.2 Guide to This Chapter2.3 General Instruction Addressing2.4 Special Instruction Addressing2.5 Bit

Keep safety first in your circuit designs!Notes regarding these materials1.Renesas Technology Corporation puts the maximum effort into making semicond

22Chapter 2 Addressing Modes2.1 Addressing ModesThis section describes addressing mode-representing symbols and operations for each addressing mode.

23Chapter 2 Addressing Modes2.2 Guide to This ChapterThe following shows how to read this chapter using an actual example.Address register relatived

24Chapter 2 Addressing Modes#IMM#IMM8#IMM16#IMM20ImmediateThe immediate data indicated by #IMMis the object to be operated on.Register directR0LR0HR1

25Chapter 2 Addressing ModesaddressaddressAddress register relativedsp:8[A0]dsp:8[A1]dsp:16[A0]dsp:16[A1]dsp:8[SB]dsp:16[SB]SB relativeFB relativedsp

26Chapter 2 Addressing Modesdsp:8[SP]Stack pointer relativedspdspSPRegisterMemoryIf the dsp value is negativeIf the dsp value is positiveaddress2.3

27Chapter 2 Addressing Modes20-bit absoluteabs20abs20dsp:20[A0]dsp:20[A1]Address register relative with20-bit displacementaddressA0LDE, STE instructi

28Chapter 2 Addressing Modes 32-bit register directR2R0R3R1A1A0 SHL, SHA instructionsJMPI, JSRI instructionsR2R0R3R1A1A0b0b31b15b16R2R0R3R1b0b31b15b1

29Chapter 2 Addressing Modes +0 dsp +7Memorylabel Program counter relativelabel Base address dspdspdsplabellabelMemory Base addressIf the dsp va

30Chapter 2 Addressing ModesThe specified register bit is the objectto be operated on.For the bit position (bit) you canspecify 0 to 15.Register dire

31Chapter 2 Addressing Modesbaseaddress Address register relativebase:8[A0]base:8[A1]base:16[A0]base:16[A1]SB relativebit,base:8[SB]bit,base:11[SB]bi

A table of symbols, a glossary, and an index are appended at the end of this manual.Using This ManualThis manual is written for the M16C/60, M16C/20,

32Chapter 2 Addressing Modesaddress FB relativebit,base:8[FB]FBaddressRegisterbasebaseIf the base value is negative If the base value is positive Mem

Chapter 3Functions3.1 Guide to This Chapter3.2 Functions

343.1 Guide to This ChapterChapter 3 Functions[ Operation ]dest src92MOVeMOV[ Function ][ Reated Instruction]LDE,STE,XCHG[ Description Exam

353.1 Guide to This ChapterChapter 3 Functions(1) MnemonicIndicates the mnemonic explained in this page.(2) Instruction code/Number of CyclesIndic

363.1 Guide to This ChapterChapter 3 Functions9292MOVeMOVsrc destR0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3A0/A0 A1/A1 [A0] [A1] A0/A0

373.1 Guide to This ChapterChapter 3 Functions(4) OperationExplains the operation of the instruction using symbols.(5) FunctionExplains the functi

383.1 Guide to This ChapterChapter 3 FunctionsThe following explains the syntax of each jump instruction—JMP, JPMI, JSR, and JSRI by using an actual

393.2 FunctionsChapter 3 FunctionsAbsolute valueABSolute[ Syntax ]ABS.size destABS.B R0LABS.W A0[ Selectable dest ]ABS[ Function ]• This instructi

403.2 FunctionsChapter 3 Functions[ Instruction Code/Number of Cycles ]Page=Add with carryADdition with Carry[ Related Instructions ] ADCF,ADD,SBB

413.2 FunctionsChapter 3 FunctionsAdd carry flagADdition Carry Flag[ Selectable dest ]destR0L/R0 R0H/R1 R1L/R2 R1H/R3A0/A0 A1/A1 [A0] [A1]dsp:8[A0

M16C Family Documents The following documents were prepared for the M16C family. (1) Document ContentsShort Sheet Hardware overviewData

423.2 FunctionsChapter 3 FunctionsAdd without carryADDition[ Related Instructions ] ADC,ADCF,SBB,SUBADD ADD[ Syntax ]ADD.size (:format) src,dest[

433.2 FunctionsChapter 3 Functions[src/dest Classified by Format]src destR0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3A0/A0 A1/A1 [A0] [

443.2 FunctionsChapter 3 FunctionsUIOBSZDCAdd & conditional jumpADdition then Jump on Not ZeroADJNZ.W #–1,R0,label[ Related Instructions ] SBJ

453.2 FunctionsChapter 3 FunctionsANDLogically AND[ Related Instructions ] OR,XOR,TST[ Function ]AND AND[ Syntax ]AND.size (:format) src,dest[ Sel

463.2 FunctionsChapter 3 Functions[src/dest Classified by Format]G formatsrc destR0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3A0/A0*1A1/

473.2 FunctionsChapter 3 Functions• This instruction logically ANDs the C flag and src together and stores the result in the C flag.Bit AND carry

483.2 FunctionsChapter 3 FunctionsBit CLeaRClear bit[ Syntax ]BCLR (:format) dest[ Related Instructions ] BSET,BNOT,BNTST,BTST,BTSTC,BTSTS[ Funct

493.2 FunctionsChapter 3 FunctionsCndConditionExpressionCndConditionExpressionGEU/C C=1 Equal to or greater than LTU/NC C=0 Smaller thanC flag is

503.2 FunctionsChapter 3 FunctionsBit Not AND carry flagLogically AND inverted bits[ Related Instructions ] BAND,BOR,BXOR,BNOR,BNXOR[ Function ]BN

51Chapter 3 Functions3.2 Functions[ Instruction Code/Number of Cycles ]Page=Bit Not OR carry flagLogically OR inverted bits[ Syntax ]BNOR src[ Desc

A-1Table of ContentsChapter 1 Overview ___________________________________________________1.1 Features of M16C/60, M16C/20, M16C/Tiny series

52Chapter 3 Functions3.2 FunctionsUIOBSZDCBit NOTInvert bit [ Syntax ]BNOT(:format) dest[ Flag Change ][ Description Example ]BNOT flagBNOT 4,Ram:

53Chapter 3 Functions3.2 FunctionsBit Not TeSTTest inverted bit[ Flag Change ][ Description Example ][ Function ][ Selectable src ]BNTST BNTST[ Syn

54Chapter 3 Functions3.2 FunctionsBit Not eXclusive OR carry flagExclusive OR inverted bits[ Flag Change ][ Description Example ][ Related Instruct

55Chapter 3 Functions3.2 FunctionsBit OR carry flagLogically OR bits[ Syntax ]BOR src[ Description Example ][ Related Instructions ] BAND,BXOR,BNAN

56Chapter 3 Functions3.2 FunctionsBReaKDebug interruptBRK[ Description Example ][ Related Instructions ] INT,INTO[ Function ]BRK BRK[ Flag Change ]

57Chapter 3 Functions3.2 FunctionsBit SETSet bit [ Flag Change ][ Related Instructions ] BCLR,BNOT,BNTST,BTST,BTSTC,BTSTS[ Function ][ Selectable

58Chapter 3 Functions3.2 FunctionsBit TeSTTest bit[ Flag Change ][ Function ][ Related Instructions ] BCLR,BSET,BNOT,BNTST,BTSTC,BTSTS[ Selectable

59Chapter 3 Functions3.2 FunctionsBit TeST & ClearTest bit & clear[ Flag Change ][ Description Example ][ Related Instructions ] BCLR,BSET,

60Chapter 3 Functions3.2 FunctionsBit TeST & SetTest bit & set[ Flag Change ][ Description Example ][ Related Instructions ] BCLR,BSET,BNOT

613.2 FunctionsChapter 3 FunctionsBit eXclusive OR carry flagExclusive OR bits[ Flag Change ][ Description Example ][ Related Instructions ] BAND,B

A-2Chapter 2 Addressing Modes ___________________________________________2.1 Addressing Modes ...

623.2 FunctionsChapter 3 Functions[ Instruction Code/Number of Cycles ]Page= Compare[ Syntax ]CMP.size (:format) src,dest[ Description Example ][ S

633.2 FunctionsChapter 3 Functions[src/dest Classified by Format]S format*3src destR0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3A0/A0 A1/

643.2 FunctionsChapter 3 FunctionsDecimal ADdition with CarryDecimal add with carry[ Syntax ]DADC.size src,dest[ Flag Change ][ Description Example

653.2 FunctionsChapter 3 FunctionsDecimal ADDitionDecimal add without carry[ Flag Change ][ Description Example ]DADD.B #3,R0LDADD.W R1,R0[ Related

663.2 FunctionsChapter 3 FunctionsUIOBSZDCDECrementDecrement[ Syntax ]DEC.size dest[ Flag Change ][ Related Instructions ] INC[ Function ]DEC DEC[

673.2 FunctionsChapter 3 FunctionsSigned divideDIVideDIV.B A0 ;A0’s 8 low-order bits is the divisor.DIV.B #4DIV.W R0[ Related Instructions ] DIVU,D

683.2 FunctionsChapter 3 FunctionsDIVide UnsignedUnsigned divide[ Description Example ][ Related Instructions ] DIV,DIVX,MUL,MULUDIVU DIVU[ Syntax

693.2 FunctionsChapter 3 FunctionsDIVide eXtensionSinged divide[ Syntax ]DIVX.size src[ Description Example ][ Related Instructions ] DIV,DIVU,MUL,

703.2 FunctionsChapter 3 FunctionsDecimal SuBtract with BorrowDecimal subtract with borrow[ Syntax ]DSBB.size src,dest[ Flag Change ][ Description

713.2 FunctionsChapter 3 FunctionsDecimal SUBtractDecimal subtract without borrow [ Syntax ]DSUB.size src,dest [ Flag Change ] [ Description Exa

Quick Reference-1DIVUDIVXDSBBDSUBENTEREXITDEXTSFCLRFSETINCINTINTOJCnd JEQ/Z JGE JGEU/C JGT JGTU JLE JLEU JLT JLTU/NC JN

72Chapter 3 Functions3.2 Functions179ENTER functionBuild stack frame[ Description Example ]ENTER #3[ Related Instructions ] EXITDENTER ENTER[ Flag

73Chapter 3 Functions3.2 FunctionsArgument of function[ Instruction Code/Number of Cycles ]Page=180EXIT and Deallocate stack frame[ Description Exa

74Chapter 3 Functions3.2 FunctionsEXTend SignExtend sign[ Description Example ][ Function ][ Flag Change ]EXTS EXTS[ Syntax ]EXTS.size dest• This i

75Chapter 3 Functions3.2 FunctionsFlag register CLeaRClear flag register bit[ Flag Change ][ Description Example ][ Related Instructions ] FSET[ Fu

76Chapter 3 Functions3.2 FunctionsFlag register SETSet flag register bit[ Description Example ][ Related Instructions ] FCLR[ Function ][ Selectabl

77Chapter 3 Functions3.2 FunctionsINCrementIncrement[ Description Example ]INC.W A0INC.B R0L[ Related Instructions ] DEC[ Function ][ Selectable de

78Chapter 3 Functions3.2 FunctionsInterrupt by INT instructionINTerrupt[ Related Instructions ] BRK,INTO[ Flag Change ]INT INT[ Syntax ]INT src[ De

79Chapter 3 Functions3.2 FunctionsINTerrupt on OverflowInterrupt on overflow[ Syntax ]INTO[ Related Instructions ] BRK,INT[ Flag Change ]INTO INTO[

80Chapter 3 Functions3.2 FunctionsCndConditionExpressionCndConditionExpressionGEU/C C=1 Equal to or greater than LTU/NC C=0 Smaller thanC flag is 1

81Chapter 3 Functions3.2 FunctionsJuMPUnconditional jump[ Syntax ]JMP(.length) label[ Description Example ][ Related Instructions ] JMPI,JMPSJMP JM