Renesas Renasas Single-Chip Microcomputer SH7086 Bedienungsanleitung PDF herunterladen (Seite 22)

Chapter 1 Overview

1.3 Register Configuration

The central processing unit (CPU) contains the 13 registers shown in Figure 1.3.1. Of these registers, R0,

R1, R2, R3, A0, A1, and FB each consist of two sets of registers configuring two register banks.

1.3.1 Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)

The data registers (R0, R1, R2, and R3) consist of 16 bits, and are used primarily for transfers and

arithmetic/logic operations.

Registers R0 and R1 can be halved into separate high-order (R0H, R1H) and low-order (R0L, R1L) parts

for use as 8-bit data registers. For some instructions, moreover, you can combine R2 and R0 or R3 and

R1 to configure a 32-bit data register (R2R0 or R3R1).

b15 b8b7 b0

b15 b0











b15 b0











b19 b0

INTB H L

b19 b0

b15 b0

USP

b15 b0

ISP

b15 b0

FLG

IPL U I O B S Z D C

*1 These registers have two register banks.

Frame

base

Data

registers

Address

registers

Program

counter

Interrupt table

User stack

pointer

Interrupt stack

pointer

Static base

Flag register

Figure 1.3.1 CPU register configuration

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 307 308

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