Renesas Renasas Single-Chip Microcomputer SH7086 Bedienungsanleitung PDF herunterladen (Seite 284)

266

6.1

Instruction queue buffer

Calculation number of cycles

6.1 Instruction queue buffer

The M16C/60, M16C/20, M16C/Tiny series have 4-stage (4-byte) instruction queue buffers. If the instruc-

tion queue buffer has a free space when the CPU can use the bus, instruction codes are taken into the

instruction queue buffer. This is referred to as “prefetch”. The CPU reads (fetches) these instruction codes

from the instruction queue buffer as it executes a program.

Explanation about the number of cycles in Chapter 4 assumes that all the necessary instruction codes are

placed in the instruction queue buffer, and that data is read or written to the memory connected via a 16-bit

________

bus (including the internal memory) beginning with even addresses without software wait or RDY or other

wait states. In the following cases, more cycles may be needed than the number of cycles shown in this

manual:

• When not all of the instruction codes needed by the CPU are placed in the instruction queue buffer...

Instruction codes are read in until all of the instruction codes required for program execution are avail-

able. Furthermore, the number of read cycles increases in the following cases:

(1) The number of read cycles increases as many as the number of wait cycles incurred when reading

________

instruction codes from an area in which software wait or RDY or other wait states exist.

(2) When reading instruction codes from memory chips connected to an 8-bit bus, more read cycles are

required than for 16-bit bus.

________

• When reading or writing data to an area in which software wait or RDY or other wait states exist...

The number of read or write cycles increases as many as the number of wait cycles incurred.

• When reading or writing 16-bit data to memory chips connected to an 8-bit bus...

The memory is accessed twice to read or write one 16-bit data. Therefore, the number of read or write

cycles increases by one for each 16-bit data read or written.

• When reading or writing 16-bit data to memory chips connected to a 16-bit bus beginning with an odd

address...

The memory is accessed twice to read or write one 16-bit data. Therefore, the number of read or write

cycles increases by one for each 16-bit data read or written.

Note that if prefetch and data access occur in the same timing, data access has priority. Also, if more than

three bytes of instruction codes exist in the instruction queue buffer, the CPU assumes there is no free

space in the instruction queue buffer and, therefore, does not prefetch instruction code.

Figures 6.1.1 to 6.1.8 show examples of instruction queue buffer operation and CPU execution cycles.

1 2 ... 279 280 281 282 283 284 285 286 287 288 289 ... 307 308

Keine Kommentare

Renesas Renasas Single-Chip Microcomputer SH7086 Bedienungsanleitung Seite 284