Renesas User System Interface Board HS7047ECH61H Bedienungsanleitung PDF herunterladen (Seite 221)

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5.4 Executing Your Program

5.4.1 Step Execution

Break conditions are ignored during step execution, but trigger pulses will be output.

5.5 Event Functions

5.5.1 Software Breakpoints

• A software breakpoint is realized by replacing the instruction at the specified address with a special

instruction. Accordingly, it can only be set to the area including the emulation RAM. Note that it cannot be

set to the following addresses:

⎯ Addresses whose memory content is H'0000

• Do not modify the contents of the software breakpoints addresses by the user program.

• The content of a software breakpoint address is replaced by a break instruction during user program

execution.

• The maximum number of software breakpoints and temporary PC breakpoints in [Temporary PC

Breakpoints] of the [Run Program] dialog box is 255 in total. Therefore, when 255 software breakpoints

have been set, no temporary breakpoint set in [Temporary PC Breakpoints] of the [Run Program] dialog box

is valid. Ensure that the total number of software breakpoints and temporary PC breakpoints are 255 or less.

• Do not set a breakpoint immediately after a delayed branch instruction (at a slot instruction). If this is

attempted, a slot illegal instruction interrupt will occur when the delayed branch instruction is executed, and

the break will not occur.

5.5.2 On-Chip Break

• The satisfaction count can only be set for channel 4.

• A reset point is only valid when a sequential break is enabled.

• If a sequential break and a break range ([Address Range Break]) have been specified together, only a

sequential break is enabled.

• The address and data conditions are satisfied on the bus cycles where the values on the address bus or data

bus match. Consider the following points when setting these conditions.

⎯ Longword access

Longword data is read and written in a single bus cycle. A data condition is only valid for a longword

access when specified as longword. The specified address must be a multiple of four. Note that longword

data is only valid as the size of an access.

⎯ Word access

Word data is read and written in a single bus cycle. The specified address must be a multiple of two.

Word data is only valid as the size of an access.

⎯ Byte access

Byte data is read and written in a single bus cycle. A data condition is only valid for a byte access when

specified as byte. Any address condition, both an even and odd address, are valid.

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Renesas User System Interface Board HS7047ECH61H Bedienungsanleitung Seite 221