Renesas M16C/6NK Technical Information PDF herunterladen (Seite 90)

Rev.2.10 Apr 14, 2006 page 66 of 378

REJ09B0124-0210

M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generation Circuit

8.1.3 On-chip Oscillator Clock

This clock, approximately 1 MHz, is supplied by a on-chip oscillator. This clock is used as the clock source

for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is 1 (on-chip

oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog

timer (refer to 11.1 Count Source Protective Mode).

After reset, the on-chip oscillator is turned off. It is turned on by setting the CM21 bit in the CM2 register

to 1 (on-chip oscillator clock), and is used as the clock source for the CPU and peripheral function clocks,

in place of the main clock. If the main clock stops oscillating when the CM20 bit in the CM2 register is 1

(oscillation stop, re-oscillation detection function enabled) and the CM27 bit is 1 (oscillation stop,

re-oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying the

necessary clock for the MCU.

8.1.4 PLL Clock

The PLL clock is generated PLL frequency synthesizer. This clock is used as the clock source for the

CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthesizer

is activated by setting the PLC07 bit to 1 (PLL operation). When the PLL clock is used as the clock source

for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the CM11 bit in the CM1

Before entering wait mode or stop mode, be sure to set the CM11 bit to 0 (CPU clock source is the main

clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to 0

(PLL stops). Figure 8.11 shows the Procedure to Use PLL Clock as CPU Clock Source.

The PLL clock frequency is determined by the equation below. When the PLL clock frequency is 16 MHz

or more, set the PM20 bit in the PM2 register to 0 (2 waits).

PLL clock frequency = f(XIN) ✕ (multiplying factor set by bits PLC02 to PLC00 in the PLC0 register)

(However, PLL clock frequency = 16 MHz, 20 MHz or 24 MHz

(1)

)

NOTE:

1. 24 MHz is available Normal-ver. only.

Bits PLC02 to PLC00 can be set only once after reset. Table 8.2 shows an Example for Setting PLL Clock

Frequencies.

Table 8.2 Example for Setting PLL Clock Frequencies

XIN

(MHz)

Multiply

Factor

PLL Clock

(MHz)

(1)

PLC01 PLC00

(2)

NOTES:

1. PLL clock frequency = 16 MHz , 20 MHz or 24 MHz

2. 24 MHz is available Normal-ver. only.

3. Multiply by 6 is available Normal-ver. only.

PLC02

(3)

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