Renesas M16C/6NK Technical Information PDF herunterladen (Seite 384)

Rev.2.10 Apr 14, 2006 page 360 of 378

REJ09B0124-0210

M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Notes

23.13 A/D Converter

Set the ADCON0 (except bit 6), registers ADCON1 and ADCON2 when A/D conversion is stopped (before

a trigger occurs). After stopping A/D conversion, the VCUT bit in the ADCON1 register is changed from 1

(VREF connected) to 0 (VREF not connected),

When the VCUT bit is changed from 0 to 1, start A/D conversion after passing 1 µs or longer.

To prevent noise-induced device malfunction or latch-up, as well as to reduce conversion errors, insert

capacitors between the AVCC, VREF, and analog input pins (ANi (i = 0 to 7), AN0_i, and AN2_i) each and

the AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin.

Figure 23.4 shows the Use of Capacitors to Reduce Noise.

Make sure the port direction bits for those pins that are used as analog inputs are set to 0 (input mode).

Also, if the TGR bit in the ADCON0 register = 1 (external trigger), make sure the port direction bit for the

__________

ADTRG pin is set to 0 (input mode).

When using key input interrupt, do not use any of four pins AN4 to AN7 as analog inputs. (A key input

interrupt request is generated when the A/D input voltage goes low.)

The φAD frequency must be 10 MHz or less. Without sample and hold, limit the φAD frequency to 250 kHz

or more. With the sample and hold, limit the φAD frequency to 1 MHz or more.

When changing an A/D operating mode, select analog input pin again in bits CH2 to CH0 in the ADCON0

Figure 23.4 Use of Capacitors to Reduce Noise

VCC

VSS

MCU

ANi: ANi, AN0_i, and AN2_i (i =0 to 7)

NOTES:

1. C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF, C4 ≥ 0.1 µF (reference).

2. Use thick and shortest possible wiring to connect capacitors.

AVCC

AVSS

VREF

ANi

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