Renesas M16C/6NK Technical Information PDF herunterladen (Seite 183)

Rev.2.10 Apr 14, 2006 page 159 of 378

REJ09B0124-0210

M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface

15.1.1 Clock Synchronous Serial I/O Mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data.

Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers to

be Used in and Setting in Clock Synchronous Serial I/O Mode.

Table 15.1 Clock Synchronous Serial I/O Mode Specifications

Item Specification

Transfer data format Transfer data length: 8 bits

Transfer clock The CKDIR bit in the UiMR register = 0 (internal clock) : fj/(2(n+1))

• fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh

The CKDIR bit = 1 (external clock) : Input from CLKi pin

Transmit/receive control

_______ _______ _______ _______

Selectable from CTS function, RTS function or CTS/RTS function disabled

Transmit start condition Before transmission can start, meet the following requirements

(1)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

_______ _______

• If CTS function is selected, input on the CTSi pin = L

Receive start condition Before reception can start, meet the following requirements

(1)

• The RE bit in the UiC1 register = 1 (reception enabled)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

Interrupt request For transmission, one of the following conditions can be selected

generation timing • The UiIRS bit

(2)

= 0 (transmit buffer empty): when transferring data from the

UiTB register to the UARTi transmit register (at start of transmission)

• The UiIRS bit =1 (transmission completed): when the serial interface finished

transmitting data from the UARTi transmit register

For reception

• When transferring data from the UARTi receive register to the UiRB register (at

completion of reception)

Error detection Overrun error

(3)

This error occurs if the serial interface started receiving the next data before reading

the UiRB register and received the 7th bit of the next data

Select function • CLK polarity selection

Transfer data input/output can be selected to occur synchronously with the rising or

the falling edge of the transfer clock

• LSB first, MSB first selection

Whether to start transmitting or receiving data begins with bit 0 or begins with bit 7

can be selected

• Continuous receive mode selection

Reception is enabled immediately by reading the UiRB register

• Switching serial data logic

This function reverses the logic value of the transmit/receive data

• Transfer clock output from multiple pins selection (UART1)

The output pin can be selected in a program from two UART1 transfer clock pins that

have been set

_______ _______

• Separate CTS/RTS pins (UART0)

_________ _________

CTS0 and RTS0 are input/output from separate pins

i = 0 to 2

NOTES:

1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0

(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the

external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising edge

and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.

2. Bits U0IRS and U1IRS are bits 0 and 1 in the UCON register; the U2IRS bit is bit 4 in the U2C1 register.

3. If an overrun error occurs, the receive data of UiRB register will be undefined. The IR bit in the SiRIC register

remains unchanged.

1 2 ... 178 179 180 181 182 183 184 185 186 187 188 ... 411 412

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