
Rev.2.10 Apr 14, 2006 page 324 of 378
REJ09B0124-0210
M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electric Characteristics (Normal-ver.)
Figure 22.17 Timing Diagram (5)
Read timing
Write timing
BCLK
CSi
ALE
DBi
ADi
BHE
WR, WRL
WRH
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting and external area access)
BCLK
CSi
ALE
DBi
ADi
BHE
RD
tcyc
t
d(BCLK-CS)
30ns.max
t
d(BCLK-AD)
30ns.max
t
d(BCLK-ALE)
30ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-RD)
30ns.max
Hi-Z
t
SU(DB-RD)
50ns.min
t
h(RD-DB)
0ns.min
t
h(BCLK-RD)
0ns.min
t
h(RD-AD)
0ns.min
t
h(BCLK-AD)
4ns.min
t
h(BCLK-CS)
4ns.min
tcyc
Hi-Z
t
d(BCLK-CS)
30ns.max
t
d(BCLK-AD)
30ns.max
t
d(BCLK-ALE)
30ns.max
t
h(BCLK-ALE)
-4ns.min
t
d(BCLK-WR)
30ns.max
t
h(BCLK-CS)
4ns.min
t
h(BCLK-AD)
4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-WR)
0ns.min
t
d(BCLK-DB)
40ns.max
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
t
h(BCLK-DB)
4ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
t
ac2(RD-DB)
(2.5 ✕ tcyc-60)ns.max
tcyc =
1
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : V
IL
= 0.6 V, V
IH
= 2.7 V
Output timing voltage : V
OL
= 1.65 V, V
OH
= 1.65 V
VCC = 3.3 V
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