Renesas H8S/2628 Technical Information PDF herunterladen (Seite 391)

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8.1.8 Signals to Indicate Bus States and Areas

The following tables show examples of signals to indicate the bus states and areas that can be acquired by the

emulator.

Table 8.7 Bus State Signals Acquired by the Emulator

Bus State Trace Display (Status) Description

CPU Prefetch PROG CPU prefetch cycles

CPU Data DATA CPU data access cycles

Refresh REFRESH Refresh cycles

DMAC DMAC DMAC cycles

DTC DTC DTC cycles

Other OTHER Others

Table 8.8 Area Signals Acquired by the Emulator

Area Trace Display (Area) Description

On-chip ROM ROM ROM

On-chip RAM RAM RAM

On-chip I/O 16bit I/O-16 16-bit I/O

On-chip I/O 8bit I/O-8 8-bit I/O

External 16bit EXT-16 16-bit EXT (external)

External 8bit EXT-8 8-bit EXT (external)

DTC RAM RAM/DTC DTCRAM

Note: The signals to indicate bus states and areas are used to set the [Bus/Area] condition of the event point.

They can also be acquired as the trace information. The bus state signals are also used to set the

condition not to acquire the trace ([Suppress] option) and in the Access Count Of Specified Range

Measurement mode for measuring the hardware performance ([Access Type] option).

8.1.9 Monitoring Function

This emulator incorporates the bus monitoring circuit as the standard, which thus allows a use of the monitoring

function to update the content of memory without affecting the realtime operation.

8.1.10 Trigger Points

This emulator incorporates the bus monitoring circuit as the standard, which thus allows a use of trigger points

that can be set on the [Trigger] sheet in the [Event] window.

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