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Rev. 3.0, 09/98, page 242 of 361
11.4 Interrupts
The A/D conversion module generates an A/D-end interrupt request (ADI) at the end of A/D
conversion.
The ADI interrupt request can be enabled or disabled by the ADIE bit in the A/D control/status
register (ADCSR).
- Renesas Technology Corp 1
- Hardware Manual 2
- Cautions 3
- Contents 5
- Section 4 Exception Handling 6
- Section 6 I/O Ports 6
- Section 8 8-Bit Timers 7
- Section 9 PWM Timers 8
- Section 11 A/D Converter 8
- Section 12 D/A Converter 9
- Section 13 RAM 9
- Section 14 ROM 9
- Section 15 Power-Down State 10
- Appendix B Register Field 10
- Hardware Standby Mode 11
- Appendix E Package Dimensions 11
- Appendix C Pin States 11
- Section 1 Overview 12
- Table 1.1 Features 13
- Table 1.1 Features (cont) 14
- 1.2 Block Diagram 15
- 1.3.1 Pin Arrangement 16
- 1.3.2 Pin Functions 19
- Table 1.3 Pin Functions 22
- Section 2 CPU 26
- Figure 2.1 CPU Registers 27
- Unused area 28
- Stack area 28
- 2.3 Addressing Modes 30
- 2.4 Data Formats 36
- 2.5 Instruction Set 39
- Operation Notation 40
- 2.5.2 Arithmetic Operations 43
- 2.5.5 Bit Manipulations 46
- 2.5.6 Branching Instructions 50
- Op: Operation field 54
- 3.1 Overview 64
- 3.4 Address Space Map 68
- 4.1 Overview 71
- 4.2 Reset 71
- 4.3 Interrupts 74
- Table 4.2 Interrupts 75
- 4.4 Note on Stack Handling 86
- 5.1 Overview 87
- 5.2 Oscillator Circuit 88
- XTAL and EXTAL pins 89
- 5.3 System Clock Divider 90
- Section 6 I/O Ports 91
- Table 6.1 Port Functions 92
- 6.2 Port 1 94
- 6.3 Port 2 98
- Internal data bus 101
- Internal address bus 101
- 6.4 Port 3 102
- 6.5 Port 4 106
- , and P4 109
- 6.6 Port 5 110
- 6.7 Port 6 115
- 6.8 Port 7 121
- 6.9 Port 8 123
- 7.1 Overview 137
- Module data bus 138
- Bus interface 138
- 7.2 Register Descriptions 140
- 7.3 CPU Interface 153
- 7.4 Operation 156
- FRC clock pulse 157
- Internal input 158
- Input at FTI pin 158
- 7.5 Interrupts 162
- 7.6 Sample Application 163
- 7.7 Application Notes 164
- Section 8 8-Bit Timers 168
- 8.2 Register Descriptions 171
- (TCSR) is set to “1.” 173
- Bit:76543210 177
- MPE ICKS1 ICKS0 177
- Initial value:11111000 177
- Read/Write: R/W R/W R/W 177
- 8.3 Operation 178
- 8.4 Interrupts 182
- 8.5 Sample Application 182
- 8.6 Application Notes 183
- Section 9 PWM Timers 188
- 9.2 Register Descriptions 190
- 9.3 Operation 193
- 9.4 Application Notes 195
- 10.1 Overview 196
- 10.1.4 Register Configuration 198
- Table 10.2 SCI Registers 198
- 10.2 Register Descriptions 199
- 10.3 Operation 214
- “0” D0 D1 D2 D3 D4 217
- One frame 217
- D5 D6 D7 0/1 “1” “1” 217
- Select communication 218
- 10.4 Interrupts 233
- 10.5 Application Notes 233
- Section 11 A/D Converter 236
- 11.1.2 Block Diagram 237
- 11.2 Register Descriptions 239
- 11.3 Operation 243
- 01100001 244
- 01110010 246
- 11.4 Interrupts 251
- Section 12 D/A Converter 252
- 12.2 Register Descriptions 255
- 12.3 Operation 257
- Section 13 RAM 258
- 13.4 Operation 259
- Section 14 ROM 260
- Package Socket Adapter 262
- 84-pin PLCC HS338ESC02H 262
- 80-pin QFP HS338ESH02H 262
- 14.3 Programming 266
- = 6.0V ±0.25V, V 269
- Item Value 272
- Minimum illumination 15W⋅s/cm 272
- Manufacturer Code 273
- Section 15 Power-Down State 274
- 15.3 Sleep Mode 277
- 15.5 Hardware Standby Mode 281
- 16.1 Absolute Maximum Ratings 283
- 16.3.1 Bus Timing 296
- 16.3.2 Control Signal Timing 298
- (1) Reset Input Timing 298
- (2) Interrupt Input Timing 298
- (3) Clock Settling Timing 299
- , FTIB 300
- 16.3.7 I/O Port Timing 303
- A.1 Instruction Set List 304
- A.2 Operation Code Map 312
- Table A.2 Operation Code Map 313
- Appendix B Register Field 320
- D/A: D/A converter 321
- TMR1: 8-Bit Timer channel 1 322
- B.2 Register Descriptions 324
- H'FFE4, H'FFE6 360
- Appendix C Pin States 363
- Table C.1 Pin States (cont) 364
- Unit: mm 366
- H8/338 Series Hardware Manual 369
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