
Rev. 3.0, 09/98, page 193 of 361
Bit 3Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in the
synchronous mode.
Bit 3
STOP Description
0 One stop bit. (Initial value)
Transmit: One stop bit is added.
Receive: One stop bit is checked to detect framing errors.
1 Two stop bits.
Transmit: Two stop bits are added.
Receive: The first stop bit is checked to detect framing errors. If the second stop bit is
a space (0), it is regarded as the next start bit.
Bit 2Multiprocessor Mode (MP): This bit selects the multiprocessor format in asynchronous
communication. When multiprocessor format is selected, the parity settings of the parity enable
bit (PE) and parity mode bit (O/E) are ignored. The MP bit is ignored in synchronous
communication.
The MP bit is valid only when the MPE bit in the serial/timer control register (STCR) is set to “1.”
When the MPE bit is cleared to “0,” the multiprocessor communication function is disabled
regardless of the setting of the MP bit.
Bit 2
MP Description
0 Multiprocessor communication function is disabled. (Initial value)
1 Multiprocessor communication function is enabled.
Bits 1 and 0Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source when the baud rate generator is clocked from within the chip.
Bit 1
CKS1
Bit 0
CKS0 Description
00φ clock (Initial value)
01φ/4 clock
10φ/16 clock
11φ/64 clock
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