Renesas 70 Technical Information Seite 47
- Seite / 49
- Inhaltsverzeichnis
- LESEZEICHEN
- To our customers 1
- MOS INTEGRATED CIRCUIT 3
- APPLICATIONS 4
- PIN CONFIGURATION (Top View) 4
- INTERNAL BLOCK DIAGRAM 6
- 2. PIN FUNCTIONS 9
- 2.1 Port Pins 9
- Data Sheet U13189EJ5V1DS 10
- 2.2 Non-Port Pins 11
- DD or VSS via a resistor 13
- 3. ELECTRICAL SPECIFICATIONS 16
- 3.1 Normal Operation Mode 16
- °C, VDD = VSS = 0 V) 17
- High-speed CMOS inverter 18
- External clock 18
- A = 25°C and VDD = 5.0 V 19
- °C, VDD = VDDDR) 21
- Test points 23
- (2) Input wave 25
- (b) Other than (a) 25
- OR 10 ns 26
- OF 10 ns 26
- WRSH 500 ns 26
- (6) Write timing (1/2) 29
- Remarks 1. T = tCYK 29
- (7) Bus hold timing (1/2) 31
- (7) Bus hold timing (2/2) 32
- (8) Interrupt timing 33
- Remark T = tCYK 33
- (9) CSI timing (2/2) 35
- (ii) CSI3 timing 35
- (10) RPU timing 36
- ±10%, VSS = AVSS = 0 V)) 39
- 4. PACKAGE DRAWING 42
- Recommended 44
- NOTES FOR CMOS DEVICES 46
- Regional Information 48
- M8E 02. 11-1 49
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