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Renesas PROM Programming Adapters PCA7438F-64A Spezifikationen Seite 30

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Seitenansicht 29
Rev.2.40 Jun 14, 2004 page 30 of 56
38C1 Group
LCD DRIVE CONTROL CIRCUIT
The 38C1 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
•
LCD display register
•
Segment output enable register
•
LCD mode register
•
Selector
•
Timing controller
•
Common driver
•
Segment driver
•
Bias control circuit
A maximum of 25 segment output pins and 4 common output pins
can be used.
Up to 100 pixels can be controlled for LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register,
Fig. 29 Structure of segment output enable register and LCD mode register
the segment output enable register and the LCD display register,
the LCD drive control circuit starts reading the display data auto-
matically, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
Table 7. Maximum number of display pixels at each duty ratio
Maximum number of display pixel
25 dots
or 8 segment LCD 3 digits
50 dots
or 8 segment LCD 6 digits
75 dots
or 8 segment LCD 9 digits
100 dots
or 8 segment LCD 12 digits
Duty ratio
1
2
3
4
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
s
b
3
b
2
b
1
b
0
0
0
0
0:
S
E
G8–
S
E
G1
6
E
n
a
b
l
e
d
0
0
0
1:
S
E
G
4–
S
E
G1
6
E
n
a
b
l
e
d
0
0
1
0:
S
E
G
2–
S
E
G1
6
E
n
a
b
l
e
d
0
0
1
1:
S
E
G
1–
S
E
G1
6
E
n
a
b
l
e
d
0
1
✕
✕ :
S
E
G
0–
S
E
G1
6
E
n
a
b
l
e
d
1
0
0
0:
S
E
G0–
S
E
G1
7
E
n
a
b
l
e
d
1
0
0
1:
S
E
G
0–
S
E
G1
8
E
n
a
b
l
e
d
1
0
1
0:
S
E
G
0–
S
E
G1
9
E
n
a
b
l
e
d
1
0
1
1:
S
E
G
0–
S
E
G2
0
E
n
a
b
l
e
d
1
1
0
0:
S
E
G
0–
S
E
G2
1
E
n
a
b
l
e
d
1
1
0
1:
S
E
G
0–
S
E
G2
2
E
n
a
b
l
e
d
1
1
1
0:
S
E
G
0–
S
E
G2
3
E
n
a
b
l
e
d
1
1
1
1:
S
E
G
0–
S
E
G2
4
E
n
a
b
l
e
d
N
o
t
u
s
e
d
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
s
e
b
i
t
s
)
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
r
e
g
i
s
t
e
r
(
S
E
G
:
a
d
d
r
e
s
s
0
0
3
8
1
6,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
01
6)
b
7
b
0
L
C
D
m
o
d
e
r
e
g
i
s
t
e
r
(
L
M
:
a
d
d
r
e
s
s
0
0
3
9
1
6,
i
n
i
t
i
a
l
v
a
l
u
e
:
0
01
6)
D
uty rat
i
o se
l
ect
i
on
bi
ts
b1b0
0 0 : 1 duty (static)
0 1 : 2 duty
1 0 : 3 duty
1 1 : 4 duty
Bias control bit (Note 2)
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used
(Do not write “1” to this bit.)
LCD circuit divider division ratio selection bits
b6b5
0 0 : Clock input
0 1 : 2 division of Clock input
1 0 : 4 division of Clock input
1 1 : 8 division of Clock input
LCDCK count source selection bit (Note 3)
0 : f(X
CIN)/32
1 : φ
SOURCE/8192
N
otes 1:
S
et t
h
e
di
rect
i
on reg
i
ster o
f
t
h
e port w
hi
c
h
i
s a
l
so use
d
as t
h
e segment output ena
bl
e
d
p
i
n to
“
1
”
.
2: When “1 duty” is selected by the duty ratio selection bit, set the bias control bit to “1”.
3: LCDCK is a clock for a LCD timing controller.
b
7
b
0
(N
ote 1
)
φSOURCE represents t
h
e osc
ill
at
i
on
f
requency o
f
X
IN
i
nput
i
n t
h
e m
iddl
e- an
d
hi
g
h
-spee
d
mo
d
e,
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
i
n
t
h
e
o
n
-
c
h
i
p
o
s
c
i
l
l
a
t
o
r
m
o
d
e
,
a
n
d
s
u
b
-
c
l
o
c
k
i
n
t
h
e
l
o
w
-
s
p
e
e
d
m
o
d
e
.
Seitenansicht 29
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