
Rev.2.40 Jun 14, 2004 page 19 of 56
38C1 Group
Fig. 15 Interrupt control
Fig. 16 Structure of interrupt-related registers
I
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(
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:
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s
0
0
3
1
6
,
n
t
a
v
a
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e
:
0
0
1
6
nterrupt request reg
ster 1
0
nterrupt request
t
INT
1
interrupt request bit
Not used (return “0” when read)
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 3 interrupt request bit
n
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e
r
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c
o
n
t
r
o
r
e
g
s
t
e
r
1
0
nterrupt ena
e
t
INT
1
interrupt enable bit
Not used (Do not write “1” to these bits.)
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 3 interrupt enable bit
0
:
o
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e
r
r
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p
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q
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s
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1
:
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q
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s
t
i
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s
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e
d
1 : a
ress 003
16
,
n
t
a
va
ue: 00
16
1
:
a
r
e
s
s
0
0
3
1
6
,
n
t
a
v
a
u
e
:
0
0
1
6
n
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e
r
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p
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q
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s
t
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g
s
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r
2
0
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q
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t
t
C
N
T
R
1
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T
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r
2
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d
(
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s
“
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w
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)
S
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I
/
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A
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N
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d
(
r
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n
s
“
0
”
w
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e
n
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a
d
)
2 : a
ress 003
16
,
n
t
a
va
ue: 00
16
nterrupt contro
reg
ster 2
0
nterrupt ena
e
t
CNTR
1
interrupt enable bit
Timer 2 interrupt enable bit
Not used (Do not write “1” to this bit)
Serial I/O interrupt enable bit
Key input interrupt enable bit
AD conversion interrupt enable bit
Not used (Do not write “1” to this bit)
0 :
nterrupts
sa
e
1 : Interrupts enabled
2 : a
ress 003
16
,
n
t
a
va
ue: 00
16
0 :
a
ng e
ge act
ve
1 : Rising edge active
7
0
7
0
7
0
7
0
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