Renesas PROM Programming Adapters PCA7438F-64A Spezifikationen Seite 19

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Seitenansicht 18
Rev.2.40 Jun 14, 2004 page 19 of 56
38C1 Group
Fig. 15 Interrupt control
Fig. 16 Structure of interrupt-related registers
I
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(
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b
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(
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w
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D
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:
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0
0
3
A
1
6
,
i
n
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t
i
a
l
v
a
l
u
e
:
0
0
1
6
)
I
nterrupt request reg
i
ster 1
INT
0
i
nterrupt request
bi
t
INT
1
interrupt request bit
Not used (return “0” when read)
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 3 interrupt request bit
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o
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l
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g
i
s
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r
1
INT
0
i
nterrupt ena
bl
e
bi
t
INT
1
interrupt enable bit
Not used (Do not write “1” to these bits.)
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 3 interrupt enable bit
0
:
N
o
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e
r
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p
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q
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s
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1
:
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q
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e
d
(IREQ
1 : a
dd
ress 003
C
16
,
i
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i
t
i
a
l
va
l
ue: 00
16
)
(
I
C
O
N
1
:
a
d
d
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s
s
0
0
3
E
1
6
,
i
n
i
t
i
a
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v
a
l
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e
:
0
0
1
6
)
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r
2
C
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T
R
0
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2
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(
r
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0
w
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)
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/
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N
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s
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d
(
r
e
t
u
r
n
s
0
w
h
e
n
r
e
a
d
)
(IREQ
2 : a
dd
ress 003
D
16
,
i
n
i
t
i
a
l
va
l
ue: 00
16
)
I
nterrupt contro
l
reg
i
ster 2
CNTR
0
i
nterrupt ena
bl
e
bi
t
CNTR
1
interrupt enable bit
Timer 2 interrupt enable bit
Not used (Do not write “1” to this bit)
Serial I/O interrupt enable bit
Key input interrupt enable bit
AD conversion interrupt enable bit
Not used (Do not write “1” to this bit)
0 :
I
nterrupts
di
sa
bl
e
d
1 : Interrupts enabled
(ICON
2 : a
dd
ress 003
F
16
,
i
n
i
t
i
a
l
va
l
ue: 00
16
)
0 :
F
a
lli
ng e
d
ge act
i
ve
1 : Rising edge active
b
7
b
0
b
7
b
0
b
7
b
0
b
7
b
0
Seitenansicht 18
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