Renesas PROM Programming Adapters PCA7438F-64A Spezifikationen PDF herunterladen (Seite 14)

Rev.2.40 Jun 14, 2004 page 14 of 56

38C1 Group

Fig. No.

Related SFRs

Input/OutputName

Non-Port Function

I/O Format

Table 5 List of I/O port function

COM

–COM

P00/SEG0–

P07/SEG7

SEG

–/SEG

P20/SEG17–

P27/SEG24

(LED)/KW

–

(LED)/KW

/ADKEY

–

AN3/ADKEY3

P44/AN4–

P47/AN7

P50/INT0,

P51/INT1

P52/CNTR0

P53/CNTR1

P54/SIN

P55/SOUT

P56/SCLK

P57/SRDY

P60/XCIN

P61/XCOUT

P62/TOUT

P63/φOUT

P64

Common

Input Port P0

Segment

I/O Port P2

I/O Port P3

A/D

conversion

input

I/O Port P4

I/O Port P5

I/O port P6

Output

Input,

individual bits

Output

Input/output

individual bits

Input/output

individual bits

Input

Input/output

individual bits

Input/output

individual bits

Input/output

individual bits

LCD common output

CMOS compatible

input level

LCD segment output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

Analog input

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS compatible

input level

CMOS 3-state output

LCD segment output

Key input (key-on wake-up)

interrupt input

ADKEY input

A/D conversion input

Interrupt input

Timer X function input/output

Timer Y function input

Serial I/O function output

Sub-clock generating

circuit input/output

Timer 2 output

φ clock output

LCD mode register

PULL register

Segment output enable register

LCD0–LCD3

LCD mode register

LCD4–LCD8

PULL register

Segment output enable register

LCD8–LCD12

PULL register

Interrupt control register

A/D control register

P4 data latch

(ADKEY selected)

PULL register

A/D control register

PULL register

Interrupt edge selection register

PULL register

Timer X mode register

PULL register

Timer Y mode register

PULL register

Serial I/O control register

PULL register

CPU mode register

PULL register

Timer X mode register

PULL register

φ output control register

PULL register

(16)

(1)

(17)

(2)

(3)

(15)

(4)

(3)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(18)

Notes 1: For details of how to use double function ports as function I/O ports,refer to the applicable sections.

2: When an input level is at an intermediate potential,a current will flow from V

CC to VSS through the input-stage gate.

Especially, power source current may increase during execution of the STP and WIT instructions.

Fix the unused input pins to “H” or “L” through a resistor.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 58 59

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