
38
3851 Group
(Built-in 16 KB ROM)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 47 System clock generating circuit block diagram (Single-chip mode)
MISRG
(MISRG : address 0038
16
)
Oscillation stabilizing time set after STP
instruction released bit
Reserved bit “0”
Do not write “1“.
Not used (return “0” when read)
b7
b0
0: Automatically set “01
16
” to Timer 1,
“FF
16
” to Prescaler 12
1: Automatically set nothing
Fig. 46 Structure of MISRG
W
I
T
i
n
s
t
r
u
c
t
i
o
n
STP instruction
T
i
m
i
n
g
φ
(
i
n
t
e
r
n
a
l
c
l
o
c
k
)
S
R
Q
S
T
P
i
n
s
t
r
u
c
t
i
o
n
S
R
Q
M
a
i
n
c
l
o
c
k
s
t
o
p
b
i
t
S
R
Q
1/2 1/4
X
I
N
X
O
U
T
X
C
O
U
T
X
CIN
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
R
e
s
e
t
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
l
1/2
Port X
C
switch bit
“
1
”
“0”
Low-speed mode
High-speed or
middle-speed
mode
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits (Note)
N
o
t
e
:
A
n
y
o
n
e
o
f
h
i
g
h
-
s
p
e
e
d
,
m
i
d
d
l
e
-
s
p
e
e
d
o
r
l
o
w
-
s
p
e
e
d
m
o
d
e
i
s
s
e
l
e
c
t
e
d
b
y
b
i
t
s
7
a
n
d
6
o
f
t
h
e
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
.
W
h
e
n
l
o
w
-
s
p
e
e
d
m
o
d
e
i
s
s
e
l
e
c
t
e
d
,
s
e
t
p
o
r
t
X
c
s
w
i
t
c
h
b
i
t
(
b
4
)
t
o
“
1
”
.
Main clock division ratio
selection bits (Note)
F
F
1
6
0
1
1
6
Prescaler 12
Timer 1
Reset or
STP instruction
Timer 12 count source
selection bit
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