13
3851 Group
(Built-in 16 KB ROM)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 9 Interrupt control
Fig. 10 Structure of interrupt-related registers (1)
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
I
N
T
0
a
c
t
i
v
e
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
I
N
T
1
a
c
t
i
v
e
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
I
N
T
2
a
c
t
i
v
e
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
I
N
T
3
a
c
t
i
v
e
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
R
e
s
e
r
v
e
d
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
i
s
b
i
t
.
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
(INTEDGE : address 003A
16
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
I
N
T
0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
C
L
/
S
D
A
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
N
T
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
N
T
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
N
T
3
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
2
C
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
I
N
T
0
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
S
C
L
/
S
D
A
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
N
T
1
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
N
T
2
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
N
T
3
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
2
C
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
(
I
R
E
Q
1
:
a
d
d
r
e
s
s
0
0
3
C
1
6
)
(ICON1 : address 003E
16
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
2
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
e
r
i
a
l
I
/
O
r
e
c
e
p
t
i
o
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
e
r
i
a
l
I
/
O
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
C
N
T
R
0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
C
N
T
R
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
A
D
c
o
n
v
e
r
t
e
r
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
(
I
R
E
Q
2
:
a
d
d
r
e
s
s
0
0
3
D
1
6
)
Interrupt control register 2
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
r
e
c
e
p
t
i
o
n
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
C
N
T
R
0
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
C
N
T
R
1
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
A
D
c
o
n
v
e
r
t
e
r
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
i
s
b
i
t
)
0
:
I
n
t
e
r
r
u
p
t
s
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
s
e
n
a
b
l
e
d
(ICON2 : address 003F
16
)
0 : Falling edge active
1 : Rising edge active
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
0
:
I
n
t
e
r
r
u
p
t
s
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
s
e
n
a
b
l
e
d
b
7
b
0
b
7
b
0
b
7
b
0
b7 b0
b7 b0
(88 Seiten)
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