Renesas PCA4738L-64A Technical Information PDF herunterladen (Seite 58)

55

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3822 Group

MITSUBISHI MICROCOMPUTERS

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: X

OUT and XCOUT pins are excluded.

Serial I/O clock output “H” pulse width

Serial I/O clock output “L” pulse width

Serial I/O output delay time (Note 1)

Serial I/O output valid time (Note 1)

Serial I/O clock output rising time

Serial I/O clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

140

30

30

30

30

Symbol Parameter

Limits

Min.

ns

ns

ns

ns

ns

ns

ns

ns

Unit

tC (SCLK)/2–30

tC (SCLK)/2–30

–30

10

10

Typ. Max.

twH(SCLK)

twL(SCLK)

td(SCLK–TXD)

tv(SCLK–TXD)

tr(SCLK)

tf(SCLK)

tr(CMOS)

tf(CMOS)

(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: X

OUT and XCOUT pins are excluded.

Serial I/O clock output “H” pulse width

Serial I/O clock output “L” pulse width

Serial I/O output delay time (Note 1)

Serial I/O output valid time (Note 1)

Serial I/O clock output rising time

Serial I/O clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

350

50

50

50

50

Symbol Parameter

Limits

Min.

tC (SCLK)/2–50

tC (SCLK)/2–50

–30

20

20

Max.

twH(SCLK)

twL(SCLK)

td(SCLK–TXD)

tv(SCLK–TXD)

tr(SCLK)

tf(SCLK)

tr(CMOS)

tf(CMOS)

Typ.

Table 23 Switching characteristics 1 (Standard, One Time PROM version)

Table 24 Switching characteristics 2 (Standard, One Time PROM version)

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 81 82

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