Renesas PCA4738L-64A Technical Information Seite 33

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Seitenansicht 32
30
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3822 Group
MITSUBISHI MICROCOMPUTERS
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to 0.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Fig. 27 Block diagram of UART serial I/O
Fig. 28 Operation of UART serial I/O function
f
(
X
I
N
)
1/4
OE
P
E
F
E
1
/
1
6
1/16
D
ata
b
us
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
A
d
d
r
e
s
s
0
0
1
8
1
6
R
ece
i
ve s
hif
t reg
i
ster
R
ece
i
ve
b
u
ff
er
f
u
ll
fl
ag
(RBF)
R
ece
i
ve
i
nterrupt request
(RI)
B
au
d
rate generato
r
F
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
r
a
t
i
o
1
/
(
n
+
1
)
Add
ress 001
C
16
S
T
/
S
P
/
P
A
g
e
n
e
r
a
t
o
r
Transmit buffer register
D
a
t
a
b
u
s
T
ransm
i
t s
hif
t reg
i
ster
A
d
d
r
e
s
s
0
0
1
8
1
6
T
ransm
i
t s
hif
t reg
i
ster s
hif
t comp
l
et
i
on
fl
ag
(TSC)
T
ransm
i
t
b
u
ff
er empty
fl
ag
(TBE)
T
ransm
i
t
i
nterrupt request
(TI)
Add
ress 0019
16
S
T
d
e
t
e
c
t
o
r
S
P
d
e
t
e
c
t
o
r
UART
contro
l
reg
i
ster
Add
ress 001
B
16
C
h
a
r
a
c
t
e
r
l
e
n
g
t
h
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e
l
e
c
t
i
o
n
b
i
t
A
d
d
r
e
s
s
0
0
1
A
1
6
BRG
count source se
l
ect
i
on
bit
T
ransm
i
t
i
nterrupt source se
l
ect
i
on
bit
S
e
r
i
a
l
I
/
O
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
Cl
oc
k
contro
l
c
i
rcu
i
t
Ch
aracter
l
engt
h
se
l
ect
i
on
bi
t
7 bits
8
b
i
t
s
Serial I/O control register
P
4
6
/
S
C
L
K
S
er
i
a
l
I
/
O
status reg
i
ster
P
4
4
/
R
X
D
P
4
5
/
T
X
D
(
f
(
X
C
I
N
)
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
T
S
C
=
0
T
B
E
=
1
R
B
F
=
0
T
B
E
=
0
T
B
E
=
0
R
B
F
=
1
RBF
=1
ST
D
0
D
1
S
P
D0
D
1
S
T
SP
TBE
=1
TSC=1
ST
D
0
D
1
SP
D
0
D
1
ST
SP
T
ransm
i
t
b
u
ff
er wr
i
te s
i
gna
l
Generated at 2nd bit in 2-stop-bit mode
1
s
t
a
r
t
b
i
t
7
o
r
8
d
a
t
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b
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r
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s
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b
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(
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)
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:
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2
: T
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(
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)
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(
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)
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.
3
: T
h
e
r
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c
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v
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r
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p
t
(
R
I
)
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s
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B
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1
.
4
: A
f
t
e
r
d
a
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=
1
,
0
.
5
t
o
1
.
5
c
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=
0
.
N
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k
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