Renesas PCA4738L-64A Technical Information Seite 32

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Seitenansicht 31
29
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3822 Group
MITSUBISHI MICROCOMPUTERS
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O can be selected by setting the mode
selection bit of the serial I/O control register to 1.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Fig. 25 Block diagram of clock synchronous serial I/O
Fig. 26 Operation of clock synchronous serial I/O function
P
4
6
/
S
C
L
K
P
4
7
/
S
R
D
Y
1
P
4
4
/
R
X
D
P
4
5
/
T
X
D
f
(
X
I
N
)
1/4
1
/
4
F
/
F
Serial I/O status register
S
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
A
d
d
r
e
s
s
0
0
1
8
1
6
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
i
s
t
e
r
R
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
R
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
R
I
)
Clock control circuit
Shif
t c
l
oc
k
S
er
i
a
l
I
/
O
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
A
d
d
r
e
s
s
0
0
1
C
1
6
BRG
count source se
l
ect
i
on
bi
t
C
l
o
c
k
c
o
n
t
r
o
l
c
i
r
c
u
i
t
Falling-edge detector
D
ata
b
us
A
d
d
r
e
s
s
0
0
1
8
1
6
S
h
i
f
t
c
l
o
c
k
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
s
h
i
f
t
c
o
m
p
l
e
t
i
o
n
f
l
a
g
(
T
S
C
)
T
ransm
i
t
b
u
ff
er empty
fl
ag
(TBE)
T
ransm
i
t
i
nterrupt request
(TI)
T
ransm
i
t
i
nterrupt source se
l
ect
i
on
bi
t
A
d
d
r
e
s
s
0
0
1
9
1
6
D
a
t
a
b
u
s
A
d
d
r
e
s
s
0
0
1
A
1
6
Transmit buffer register
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
(f(X
CIN
)
i
n
l
ow-spee
d
mo
d
e
)
R
e
c
e
i
v
e
e
n
a
b
l
e
s
i
g
n
a
l
S
R
D
Y
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF
= 1
TSC = 1
T
B
E
=
0
T
B
E
=
1
T
S
C
=
0
T
rans
f
er s
hif
t c
l
oc
k
(1/2 to 1/2048 of the internal
clock, or an external clock)
S
e
r
i
a
l
o
u
t
p
u
t
T
X
D
S
e
r
i
a
l
i
n
p
u
t
R
X
D
W
r
i
t
e
s
i
g
n
a
l
t
o
r
e
c
e
i
v
e
/
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
0
0
1
8
1
6
)
O
v
e
r
r
u
n
e
r
r
o
r
(
O
E
)
d
e
t
e
c
t
i
o
n
N
o
t
e
s
1
:
T
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
(
T
I
)
c
a
n
b
e
g
e
n
e
r
a
t
e
d
e
i
t
h
e
r
w
h
e
n
t
h
e
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
h
a
s
e
m
p
t
i
e
d
(
T
B
E
=
1
)
o
r
a
f
t
e
r
t
h
e
t
r
a
n
s
m
i
t
s
h
i
f
t
o
p
e
r
a
t
i
o
n
h
a
s
e
n
d
e
d
(
T
S
C
=
1
)
,
b
y
s
e
t
t
i
n
g
t
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
T
I
C
)
o
f
t
h
e
s
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
.
2
:
I
f
d
a
t
a
i
s
w
r
i
t
t
e
n
t
o
t
h
e
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
w
h
e
n
T
S
C
=
0
,
t
h
e
t
r
a
n
s
m
i
t
c
l
o
c
k
i
s
g
e
n
e
r
a
t
e
d
c
o
n
t
i
n
u
o
u
s
l
y
a
n
d
s
e
r
i
a
l
d
a
t
a
i
s
o
u
t
p
u
t
c
o
n
t
i
n
u
o
u
s
l
y
f
r
o
m
t
h
e
T
X
D
p
i
n
.
3
:
T
h
e
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
(
R
I
)
i
s
s
e
t
w
h
e
n
t
h
e
r
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
b
e
c
o
m
e
s
1
.
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
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