Renesas V850E2 Bedienungsanleitung PDF herunterladen (Seite 38)

R01DS0148EJ0102

Data Sheet

Chapter 7 Peripherals specification

7.7.2 Slave mode

(1) CSIG timing slave mode

Table 7-3 CSIG timing (Slave mode)

Note n: Number of macro instances. Refer to the User Manual for the detailed

specification.

Parameter Symbol Condition

Ratings

Unit

Min Typ Max

Macro Operation clock cycle

time

tKCYGn 20.83 - - ns

CSIGnSC cycle time tKCYSGn 200 - - ns

CSIGnSC high level width tKWHSGn 0.5 · tKCYSGn-10 - - ns

CSIGnSC low level width tKWLSGn 0.5 · tKCYSGn-10 - - ns

CSIGnSI setup time

(vs. CSIGnSC )

tSSISGn 20 - - ns

CSIGnSI hold time

(vs. CSIGnSC)

tHSISGn tKCYGn+5.0 - - ns

SO output delay (vs SCKI) tDSOSGn - - 35 ns

CSIGnRYO output delay

CSIG4RYO output delay is not supported, because CSIG4RYO does not have output mode.

tSRYOGn - - 35 ns

_CSIGnSSI setup time

(vs. CSIGnSC)

tSSSISGn 0.5 · tKCYSn-5.0 - - ns

_CSIGnSSI hold time

(vs. CSIGnSCI)

tHSSISGn tKCY+5.0 - - ns

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