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R01DS0148EJ0102
Data Sheet
Chapter 7 Peripherals specification
7.7 CSI timing
7.7.1 Master modes
(1) CSIG timing
Table 7-2 CSIG timing (Master mode)
Note n: Number of macro instances. Refer to the User Manual for the detailed
specification.
Parameter Symbol Condition
Ratings
Unit
Min Typ Max
Macro Operation clock cycle
time
tKCYGn 20.83 - - ns
CSIGnSC cycle time tKCYMGn 100 - - ns
CSIGnSC high level width tKWHMGn 0.5 · tKCYMGn-10 - - ns
CSIGnSC low level width tKWLMGn 0.5 · tKCYMGn-10 - - ns
CSIGnSI setup time
(vs. CSIGnSC )
tSSIMGn 30 - - ns
CSIGnSI hold time
(vs. CSIGnSC)
tHSIMGn 0 - - ns
CSIGnSO output delay
(vs. CSIGnSC)
tDSOMGn - - 7 ns
CSIGnRYI setup time
(vs. CSIGnSC)
tSRYIGn
CSIGnCTL1.CSIGnSIT=x
CSIGnCTL1.CSIGnHSE=1
2 · tKCYGn+25 - - ns
CSIGnRYI High level width tWRYIGn CSIGnCTL1.CSIGnHSE=1 tKCYGn- 5.0 - - ns
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