
7540 Group
Rev.4.00 Jun 21, 2004 page 6 of 82
REJ03B0011-0400Z
Fig. 7 Functional block diagram (32P4B package)
FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B)
16
11
13
12
P1(5)
31
31
2
32
5
4
P2(6)
P3(6)
1720 18
10
14
15
9
7
8
6
0
19
2122
P0(8)
30
28 26
24
29
27
25 23
A/D
converter
(10)
X
IN OUT
X
CPU
V
SS
RESET
V
CC
CNV
SS
I/O port P2
I/O port P0
I/O port P1
I/O port P3
SI/O1(8)
RAM
ROM
A
X
Y
S
PC
H
PC
L
PS
Reset input
Clock generating circuit
Clock input
Clock output
V
REF
Watchdog timer
Reset
INT
0
SI/O2(8)
CNTR
0
Prescaler Y (8)
Prescaler Z (8)
Timer X (8)
Timer Z (8)
Timer Y (8)
Key-on wakeup
TY
OUT
TZ
OUT
Prescaler X (8)
CNTR
1
Timer A (16)
INT
0
Timer 1 (8)
Prescaler 1 (8)
TX
OUT
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