Renesas PROM Programming Adapter PCA7435FPG02 Bedienungsanleitung Seite 19

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Seitenansicht 18
7540 Group
Rev.4.00 Jun 21, 2004 page 19 of 82
REJ03B0011-0400Z
Fig. 18 Block diagram of ports (2)
Pull-up control
INT interrupt input
P3 input level
selection bit
(11) Ports P3
0
–P3
5
Pull-up control
(9) Port P1
4
Data bus
Serial I/O1 ready output
Serial I/O2 output
Serial I/O2 input
S
DATA2
pin selection bit
Port latch
Direction
register
S
DATA2
output in operation signal
CNTR
0
interrupt input
Pulse output mode
Timer output
P1
0
, P1
2
, P1
3
input level
selection bit
Serial I/O mode selection bit
Serial I/O1 enable bit
S
RDY1
output enable bit
P1
0
, P1
2
, P1
3
, P3
6
, and P3
7
input level are switched to the CMOS/TTL level by the port P1P3 control register.
Data bus
Port
latch
Direction
register
Data bus
Port
latch
Direction
register
Data bus
Port latch
Direction
register
A/D converter input
Analog input pin
selection bit
(12) Ports P3
6
, P3
7
Data bus
Port
latch
Direction
register
*
*
(10) Ports P2
0
–P2
7
*
(8) Port P1
3
When the TTL level is selected
,
there is no h
y
steresis characteristics.
Seitenansicht 18
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