Renesas PROM Programming Adapter PCA7435FPG02 Bedienungsanleitung Seite 40
- Seite / 88
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
7540 Group
Rev.4.00 Jun 21, 2004 page 40 of 82
REJ03B0011-0400Z
A/D Converter
The functional blocks of the A/D converter are described below.
[A/D conversion register] AD
The A/D conversion register is a read-only register that stores the
result of A/D conversion. Do not read out this register during an A/
D conversion.
[A/D control register] ADCON
The A/D control register controls the A/D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion comple-
tion bit. The value of this bit remains at “0” during A/D conversion,
and changes to “1” at completion of A/D conversion.
A/D conversion is started by setting this bit to “0”.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 1024, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of ports P27/AN7 to P20/AN0,
and inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores its result into the A/D
conversion register. When A/D conversion is completed, the con-
trol circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”. Because the comparator is constructed
linked to a capacitor, set f(XIN) to 500 kHz or more during A/D con-
version.
■ Note on A/D converter
As for AD translation accuracy, on the following operating condi-
tions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sensi-
tive to noise when VREF voltage is set up lower than Vcc
voltage, accuracy may become low rather than the case where
VREF voltage and Vcc voltage are set up to the same value.
Fig. 38 Structure of A/D control register
Fig. 39 Structure of A/D conversion register
Fig. 40 Block diagram of A/D converter
A
/
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
:
a
d
d
r
e
s
s
0
0
3
4
1
6,
i
n
i
t
i
a
l
v
a
l
u
e
:
1
01
6)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
A
D
c
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
i
o
n
b
i
t
0
:
C
o
n
v
e
r
s
i
o
n
i
n
p
r
o
g
r
e
s
s
1
:
C
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
e
d
b
7
b
0
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
s
0
0
0
:
P
2
0/
A
N0
0
0
1
:
P
21/
A
N1
0
1
0
:
P
22/
A
N2
0
1
1
:
P
23/
A
N3
1
0
0
:
P
24/
A
N4
1
0
1
:
P
25/
A
N5
1
1
0
:
P
26/
A
N6
(
N
o
t
e
)
1
1
1
:
P
2
7/
A
N7
(
N
o
t
e
)
N
o
t
e
:
T
h
e
s
e
c
a
n
b
e
u
s
e
d
o
n
l
y
f
o
r
3
6
p
i
n
v
e
r
s
i
o
n
.
Read 8-bit (Read only address 0035
16
)
b7 b0
b9 b8 b7 b6 b5 b4 b3 b2
(Address 0035
16
)
Read 10-bit (read in order address 0036
16
, 0035
16
)
b7
b0
b9 b8
(Address 0036
16
)
b7
b0
b7 b6 b5 b4 b3 b2 b1 b0
(Address 0035
16
)
Note: High-order 6-bit of address 0036
16
returns “0” when read.
A/D control register
(Address 0034
16)
Channel selector
A/D control circuit
Resistor ladder
VREF
Comparator
A/D interrupt request
b7 b0
Data bus
3
10
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
A/D conversion register (low-order)
(Address 0036
16)
(Address 0035
16)
A/D conversion register (high-order)
VSS
(2) When VREF voltage is lower than [3.0 V], the accuracy at the
low temperature may become extremely low compared with
that at room temperature When the system would be used at
low temperature, the use at VREF=3.0 V or more is recom-
mended.
- 7540 Group 1
- Package type: 32P6U-A 2
- M37540RSS 3
- FUNCTIONAL BLOCK 4
- PIN DESCRIPTION 7
- I/O Ports 16
- Interrupts 20
- ●Timer 1 23
- ●Timer A 23
- ●Timer X 24
- ●Timer Y 26
- ●Timer Z 28
- REJ03B0011-0400Z 33
- Serial I/O 34
- ●Serial I/O1 34
- Receive buffer register 35
- ●Serial I/O2 38
- A/D Converter 40
- Watchdog Timer 41
- Reset Circuit 42
- Clock Generating Circuit 44
- Generation Mode 50
- ■ Serial I/O 50
- ■ A/D Converter 50
- Caution: 51
- ELECTRICAL CHARACTERISTICS 52
- 1.7540Group (General purpose) 52
- SS for the mask ROM version 52
- OUT is excluded 60
- (continued) 74
- PACKAGE OUTLINE 81
- RENESAS SALES OFFICES 83
- 2/SCLK1” pin eliminated 85
- OUT pin eliminated 85
- 4 revised 86
- IN) = 6 MHz 87
- IN) = 8MHz, middle-speed mode 87
- REVISION HISTORY 88
- 7540 Group Data Sheet 88
Verwandte Produkte und Handbücher für Prozessoren Renesas PROM Programming Adapter PCA7435FPG02
Prozessoren Renesas QFP-144 Bedienungsanleitung
(16 Seiten)
(16 Seiten)
© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.057 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern