Rev. 1.0, 07/03, page 3 of 38
Section 2 SDRAM Interface Examples
2.1 SH7709S/SH7729R/SH7706 to SDRAM Interface Examples
2.1.1 SDRAM Direct Connection
Synchronous DRAM can be selected via the
CS
signal, and can be connected to areas 2 and 3 of
the physical address space in the SH7709S, SH7729R, or SH7706 by using common control
signals such as
RAS
. When the memory type bits (DRAMTP2 to DRAMTP0) of BCR1 are set to
010, area 2 and area 3 can be used as the normal memory area and synchronous DRAM area,
respectively. When the memory type bits (DRAMTP2 to DRAMTP0) of BCR1 are set to 011,
both areas 2 and 3 can be used as the synchronous DRAM area.
This LSI supports burst read/single write mode with burst length 1 as a synchronous DRAM
operating mode. The data bus width can be selected as either 16 bits or 32 bits. In cache-fill/write-
back cycles, 16-byte burst transfer is always performed. In write-through area write cycles or non-
cacheable area read/write cycles, only one access is performed.
To connect this LSI to synchronous DRAM directly, the
RAS3L
(
RASL
),
RAS3U
(
RASU
),
CASL
,
CASU
, RD/
WR
,
CS2
or
CS3
, DQMUU, DQMUL, DQMLU, DQMLL, and CKE signals are used
as control signals. These interface control signals, except for
CS2
and
CS3
, are common to each
area. In addition, the interface control signals other than CKE are valid and latched only when
CS2
or
CS3
is asserted. Accordingly, synchronous DRAM can be connected in parallel to multiple
areas. The CKE signal is negated (brought low) only when self-refreshing is performed and the
CKE signal is normally asserted (brought high).
The
RAS3L
(
RASL
),
RAS3U
(
RASU
),
CASL
, and
CASU
signal outputs are determined depending
on whether the address is in the upper or lower 32 Mbytes of each area. If the address is in the
upper 32-Mbyte area (area 2: H'0A000000 to H'0BFFFFFF, area 3: H'0E000000 to H'0FFFFFFF),
RAS3U
(
RASU
) and
CASU
are output. If it is in the lower 32-Mbyte area (area 2: H'08000000 to
H'09FFFFFF, area 3: H'0C000000 to H'0DFFFFFF),
RAS3L
and
CASL
are output. In refresh
cycles and mode-register write cycles,
RAS3L
(
RASL
) and
RAS3U
(
RASU
) or
CASU
and
CASL
are output.
The
RAS3L
(
RASL
),
RAS3U
(
RASU
),
CASL
,
CASU
and RD/
WR
signals and specific address
signals specify a command for synchronous DRAM. The synchronous DRAM commands are
NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks (PALL), row address strobe
bank active (ACVT), read (READ), read with precharge (READA), write (WRIT), write with
precharge (WRITA), and mode register setting (MRS).
(38 Seiten)
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