Renesas SH7709S Bedienungsanleitung PDF herunterladen (Seite 25)

Rev. 1.0, 07/03, page 21 of 38

Vdd

VddQ

Vss

VssQ

3.3V

GND

A15

SH7709S/SH7729R/SH7706 512-Mbit SDRAM(×16)

A14

A13

CKIO

CKE

( )

RD/

DQMLU

DQMLL

D15

BA1

BA0

A12

CLK

CKE

UDQM

LDQM

DQ15

DQ0

Figure 2.7 Interface between SDRAM (HM5257165B-A6) and SH7709S/SH7729R/SH7706

2.2 SH7727 SDRAM Interface Examples

2.2.1 SDRAM Direct Connection

Synchronous DRAM can be selected via the CS signal, and can be connected to areas 2 and 3 of

the physical address space in the SH7727 by using common control signals such as RAS. When

the memory type bits (DRAMTP2 to DRAMTP0) of BCR1 are set to 010, area 2 and area 3 can be

used as the normal memory area and synchronous DRAM area, respectively. When the memory

type bits (DRAMTP2 to DRAMTP0) of BCR1 are set to 011, both areas 2 and 3 can be used as

the synchronous DRAM area.

This LSI supports burst read/single write mode with burst length 1 as a synchronous DRAM

operating mode. The data bus width can be selected as either 16 bits or 32 bits. In cache-fill/write-

back cycles, 16-byte burst transfer is always performed. In write-through area write cycles or non-

cacheable area read/write cycles, only one access is performed.

To connect this LSI to synchronous DRAM directly, the RAS3, CAS, RD/WR, CS2 or CS3,

DQMUU, DQMUL, DQMLU, DQMLL, and CKE signals are used as control signals. These

interface control signals, except for CS2 and CS3, are common to each area. In addition, the

interface control signals other than CKE are valid and latched only when CS2 or CS3 is asserted.

Accordingly, synchronous DRAM can be connected in parallel to multiple areas. The CKE signal

is negated (brought low) only when self-refreshing is performed and the CKE signal is normally

asserted (brought high).

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