
Rev. 1.0, 07/03, page 34 of 38
Vdd
VddQ
Vss
VssQ
3.3V
GND
A15
SH7727 256-Mbit SDRAM(×16)
A14
A13
:
:
:
:
A1
CKIO
CKE
RD/
DQMLU
DQMLL
D15
D0
BA1
BA0
A12
:
:
:
:
A0
CLK
CKE
DQMU
DQML
DQ15
DQ0
Figure 2.12 Interface between SDRAM (HM5225165B-B6) and SH7727
2.2.8 HM5225165B-B6 (4 Mwords ×16 bits × 4 banks)
Bus State Controller (BSC) Settings: When two SDRAMs (HM5225165B-B6) are connected to
area 3 of the SH7727 via a 32-bit bus, the bus state controller (BSC) must be specified as
summarized below. Table 2.13 lists the BSC register settings.
Note that the interface between SDRAM and the SH7727 is performed with bus clock = 66 MHz,
CL = 2, TPC = 2, RCD = 2, TRWL = 1, and TRAS = 4.
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