Renesas SuperH SH7710 E10A Bedienungsanleitung PDF herunterladen (Seite 9)

Hybrid RISC/DSP Architecture • Floating Point Features

■ SuperH On-Chip Floating

Point Co-processor

Architectural Features

• Supports single-precision

(32 bits) and double-precision

(64 bits)

• 10-stage floating instruction

pipeline (SH-4A)

• Supports IEEE754-compliant

data types and exceptions

• Floating-point registers:

32 bits x 16 words x 2 banks

• (Single-precision x 16 words,

or double-precision x 8 words)

x 2 banks

• 32-bit CPU-FPU floating-point

communication register (FPUL)

• Supports FMAC (multiply-

and-accumulate) instruction

• Supports FDIV (divide)

and FSQRT (square root)

instructions

• Supports FLDI0/FLDI1

(load constant 0/1) instructions

• 3D graphics instructions

(single-precision only)

• 4-dimensional vector

conversion and matrix

operations (FTRV): 4 cycles

(pitch), 8 cycles (latency)

• 4-dimensional vector (FIPR)

inner product: 1 cycle (pitch),

5 cycles (latency)

• Instruction execution times

– Latency

(FMAC/FADD/FSUB/FMUL):

3 cycles (single-precision),

8 cycles (double-precision)

– Pitch

(FMAC/FADD/FSUB/FMUL):

1 cycle (single-precision),

6 cycles (double-precision)

Versatility of the floating point co-processor

Powerful 4-way FPU for 3-D graphics

16-tap, 40-sample block FIR (1.6 MACs/cycle)

STAGE 1 STAGE 4

= x + ... +

i+1

i+2

i+3

i+1

i+2

i+3

i+1

i+2

i-2

i-1

i+1

i-3

i-2

i-1

c12

c13

c14

c15

i-12

i-11

i-10

i-9

i-13

i-12

i-11

i-10

i-14

i-13

i-12

i-11

i-15

i-14

i-13

i-12

A single DIF butterfly

In1

In2

Out1

Out2

-1 W=a+jb

In1_r

In1_i

In2_r

In2_i

Out1_r

Out1_i

Out2_r

Out2_i

-b

-a

-b

-a

MULTIPLICATION

INNER PRODUCT

1024-point, radix-2 FFT (35.4 cycles)

= x

c11

c21

c31

c41

c12

c22

c32

c42

c13

c23

c33

c43

c14

c24

c34

c44

A single SuperH

instruction, FTRV,

can perform this

matrix-vector

multiplication

every 4 cycles.

Multiplication

3-D graphics

geometry

Multiplication

3-D graphics

geometry

A single SuperH instruction, FIPR, can perform this

inner-product multiplication every cycle.

ray

r1 r2

r3 0

Surface judgement

brightness

calculation

source

128-bit Floating Point Vector Engine: DSP/SIMD Instructions

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 41 42

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