Renesas SuperH SH7710 E10A Bedienungsanleitung PDF herunterladen (Seite 11)

■ Balanced power/performance

The fast speeds that SuperH devices provide would

not be usable by portable applications if the chips’

power dissipation was excessive. Therefore, Renesas

has designed the RISC and RISC/DSP devices in

low-power sub-micron CMOS processes with

low-voltage capabilities. Low static operating current

is achieved in all circuit designs; low dynamic (peak)

currents are guaranteed by logic and circuit design.

• Power-reducing techniques used in cache design

– The sense amplifiers utilize SRAM circuit-design

techniques that reduce word-line voltage swings;

this permits lower currents to be used without

sacrificing speed

– A unique cache-way-enable circuit minimizes power

demands by turning on the sense amplifiers only in that

portion of the cache that has a “hit” in a given access; this

reduces the cache data array's operating current by 75%

• Software-controlled power-reduction mechanisms:

– Each device family offers a selection of power-reduction

techniques from a palette that includes Standby and

Sleep modes, clock-speed control and selective module

shutdown

– Low operating and standby currents for longer

battery life.

■ High integration

Renesas meets the dual needs for compact devices and

low system cost by providing a broad choice of on-chip

memories and peripherals in the SuperH series.

• Large size and high performance on-chip memory:

Up to 1MB on-chip flash memory, up to 128KB

on-chip RAM, and up to 32KB instruction and

32KB data cache

• 4- to 12-channel DMAC, 2 to 5 SCIs, 16-bit and

32-bit timers (3 to 34 channels), up to 149 I/O

ports, RTC, analog interfaces (4 to 32 channels),

C, CAN (up to 2 channels), others

• All SuperH-series processors feature direct

interfaces to external memories. The on-chip

Bus State Controller, via the external bus, provides

the specialized inputs, outputs and functions for

different types, widths, and speeds of external

memory (8/16/32-bit interfaces to DRAM,

SDRAM, DDR-SDRAM, flash, ROM, etc.)

■ Best cost/performance

The SuperH architecture has a superior performance-

to-price ratio (Dhrystone MIPS/$). The architecture’s

16-bit RISC instruction set reduces system memory

requirements, which lowers the overall cost of

embedded system designs.

■ Superior floating point and DSP support

• The SuperH floating point (SH-2A, SH-4, SH-4A)

and DSP (SH2-DSP, SH3-DSP) support is built into

the processors to reduce overall system cost and

system power consumption.

• The SH-4 FPU is ideal for computer graphics and

can be utilized to efficiently implement multimedia

and networking operations.

Top Reasons To Select SuperH

JPEG image compression/expansion

processing performance:

• 10 times higher than SH-1

• 3 times higher than SH-3

JPEG compression processing time

(in seconds)

0123 54

20 MHz

SH-1

5.3

28 MHz

SH-2

3.36

60 MHz

SH-3

1.56

60 MHz

SH2-DSP

0.55

Image size (VGA): 640x480

24-bit full color

Y: Cr: Cb = 4: 2: 2

Compression ratio: 1/10

SH2-DSP Signal Processing Performance

TOP REASONS TO SELECT SuperH

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 41 42

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