
■ Serial Interface
14
M16C Platform
™
On-chip Peripherals
4
3
2
1
0
P9
3
(SS)
P9
0(CLK)
P9
1
(R
X
D
3
/ST
X
D
3
)
P9
2
(T
x
D
3
/SR
x
D
3
)
M16C(M&S)
4
3
2
1
0
P9
3
(SS)
P9
0
(CLK)
P9
1
(R
X
D
3
/ST
X
D
3
)
P9
2(TxD3/SRxD3)
4
3
2
1
0
P9
3
(SS)
P9
0(CLK)
P9
1(RXD3/STXD3)
P9
2(TxD3/SRxD3)
Por t 5
Por t 5
IC1
IC2
IC3
IC4
IC5
Por t 5
M16C(M&S)
M16C(M&S)
M16C
SI/0
IEBus
(AVC-LAN)
UART
I
2
C
CAN
RxD
TxD
CTS/RTS
CLK
Data
CLK
Data
RxD
TxD
CTS/RTS
CLK
CLKS
TxD
P9
3
(SS)
P9
0(CLK)
P9
1
(R
X
D
3
/ST
X
D
3
)
P9
2
(T
x
D
3
/SR
x
D
3
)
M16C(S)
M16C(S)
P9
3
(SS)
P9
0(CLK)
P9
1
(R
X
D
3
/ST
X
D
3
)
P9
2
(T
x
D
3
/SR
x
D
3
)
UART/Clock-Synchronous Serial I/O
The R32C/100 has nine on-chip UART/clock-synchronous
serial I/O channels
UART Function
In addition to normal UART capabilities, special functions are supported.
Gateway Function
Broad range of communication peripherals
provides gateway functionality.
Gateway Function
Synchronous Serial Communication Unit (SPI compatible)
MCU
MCU
MCU
MCU
MCU
CTS/RTS Control Capability to Connect 2 Peripheral ICs
Peripheral IC 1
Peripheral IC 2
(Does not apply to M16C/Tiny.)
Port Port Port
MCU
MCU
UART0
UART5
MCU
UART6
MCU
UART7
MCU
UART8
MCU
UART1
MCU
UART2
MCU
UART3
MCU
UART4
R32C
Ports 0 to 4 output slave select signals.
Port 5 is for the sync signal between masters.
SS low-level output selects slave operation.
: Used by master and slave.
: Used only as slave.
M&S
S
Supported MCUs
Communication control method
Start condition overlap detection
Arbitration lost detection
Slave address match determination
Initial acknowledge generation
Timeout detection function
Max. communication speed
M16C/62P, M16C/64, M32C, R32C/111
Partial software control
No detection
Requires flag to be initialized for each byte
Match determination by software
Generated by software after slave address determined
None
384 kbps
(because the SCL low-duration ≥ 1.3µs
standard is not met at faster speeds)
M16C/63, M16C/65, M16C/Tiny, R8C, R32C/118
Hardware control
Detection supported
Does not require flag to be initialized for each byte
Match determination by hardware, interrupt generated only on match
Automatic processing by hardware
Supported (dedicated timer)
400 kbps
(max. value of I
2
C Bus standard high-speed mode)
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