Renesas Emulator System M3T-MR100 Spezifikationen PDF herunterladen (Seite 12)

High-performance Embedded Workshop V.4.09 Release Note

R20UT0373EJ0100 Rev.1.00 Page 12 of 41

Feb 01, 2011

(3) Debug Settings dialog box

• Do not perform automatic target connection

The target is connected when [Debug Settings] have been completed irrespective of the setting for the [Do

not perform automatic target connection] check box on the [Options] tab.

(4) SH-4 and SH-4 with BSC simulator/debugger

• In SH-4 with BSC simulator/debugger, if the lower three bits of the source and destination addresses differ in

a DMA transfer, the last data transferred will be invalid.

e.g. SAR0=2000 DAR0=4004 DMATCR0=2 CHCR0=5491

Memory contents of address H'2000: 0102030405060708

Contents of address H'4004 after DMA transfer: 0106

• In SH-4 and SH-4 with BSC simulator/debugger, even if an instruction is modified for an address where

decoding has been completed, the pipeline is not reset and executed.

• In SH-4 with BSC simulator/debugger, if memory is accessed by a data size that differs from the size

specified by the break data, the program may not break when the break conditions are satisfied. To avoid this,

specify the same data size for the memory access data size and break data size.

• In SH-4 and SH-4 with BSC simulator/debugger, the pipeline execution for double precision FDIV and

FSQRT instructions in the SH-4 simulator/debugger is different from those in the user system. For the SH-4

simulator/debugger, one more cycle is displayed for the F3 stage pipeline.

(5) SH-3DSP simulator/debugger

• Exception code during DSP loop execution

If an exception is generated during the DSP loop execution, the exception code set in the EXPEVT

(exception event register) will differ from that described in the programming manual.

The exception code in the DSP Loop

General exception events Programming Simulator

Manual

TLB miss exception/TLB invalid exception (Read) H'070 H'040

TLB miss exception/TLB invalid exception (Write) H'070 H'060

TLB protection exception (Read) H'0D0 H'0A0

TLB protection exception (Write) H'0D0 H'0C0

CPU address error (Read) H'070 H'0E0

CPU address error (Write) H'070 H'100

• X/Y memory access conflict

If an instruction code and data are allocated to the XRAM memory (or XROM, or YROM, or YRAM), stalls

will not be generated by a conflict even if this XRAM memory is accessed by the instruction code fetch and

the MOVX or MOVY instruction in the same slot. Therefore, the number of cycles for these two types of

access will differ.

• Pipeline execution from an address other than a multiple of four

If a pipeline execution is performed from an address other than a multiple of four, the fetch stages will differ

from those described in the programming manual.

e.g. When pipeline execution is performed from an address other than a multiple of four

Programming Manual Simulator

IF IF ID EX IF ID EX

IF ID EX IF ID EX

if ID EX if ID EX

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 40 41

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