4514 Group, 4519 Group
Differences between 4514 Group and 4519 Group
REJ05B0582-0200/Rev.2.00 May 2007 Page 2 of 6
Parameter 4514 Group 4519 Group
Timer Watchdog timer At reset *7
Invalid at reset.
Watchdog timer becomes valid when
WRST instruction is executed.
Valid at reset.
Watchdog timer becomes invalid when
DWDT and WRST instructions are
executed continuously.
WRST instruction *7 (WDF1) <- 0 (WEF) <- 1
(WDF1) =1? After skipping, (WDF1) <- 0
WRST instruction
execution period
Executed until 32766 machine cycles Executed until 65534 machine cycles
RAM back-up
Invalid after system returns from RAM
back-up mode
Valid after system returns from RAM
back-up mode
A/D converter Supply voltage *8 3.0 V to 5.5 V
2.0 V to 5.5 V (MASK ROM) , 3.0 V to 5.5
V (One Time PROM)
A/D conversion clock (ADCK) INSTCK/6
INSTCK/6 , INSTCK/12 , INSTCK/24 ,
INSTCK/48
f(RING)/6 , f(RING)/12 , f(RING)/24 ,
f(RING)/48
Pin function AIN0 to AIN3 *9
Analog input-only pin
(A
IN0/CMP0- to AIN3/CMP1+)
Pin function is switched to analog input or
port input/output. (P6
0/AIN0 to P63/AIN3)
P40/AIN4 to P43/AIN7 *9
Port input/output function is active even
when analog pin functions are selected.
Pin function is switched to analog input or
port input/output.
A/D conversion time 62 machine cycles 2 machine cycles+10/f(ADCK)
Comparator comparison time 8 machine cycles 2 machine cycles+1/f(ADCK)
Voltage
comparator
Available -
Serial I/O Synchronous clock External , INSTCK/8 , INSTCK/4
External , INSTCK/8, INSTCK/4,
INSTCK/2
Port function selected Selected from 2 patterns. Selected from 4 patterns.
Reset Reset release timing
System is released from reset after f(X
IN)
counts 16892 to 16895 times.
System is released from reset after
f(RING) counts 120 to 144 times.
Built-in power-on reset circuit - Available
SRST instruction *10 - Available
Pull-up transistor in RESET pin - Available
VDCE pin = “L” Stop Stop Operation state
VDCE pin = “H” At CPU operating : operation
At RAM back-up : stop
At CPU operating : operation
At RAM back-up : operation
Voltage drop
detection circuit
Detection voltage hysteresis - Available ( typ. 0.2V)
RAM back-up
mode
P0 *11 falling edge
H leve/L level and Rising edge / falling
edge selectable
External wakeup
signal valid
waveform
P1 *11 falling edge L level
INT0, INT1 *11 H/L level
H leve/L level and Rising edge / falling
edge selectable
*12 INT0, INT1 wakeup function Always valid Valid/invalid selsctable
(106 Seiten)
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