MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
13
Fig. 6. Memory map of special function register 2 (SFR2) (2)
230
16
231
16
232
16
233
16
234
16
235
16
236
16
237
16
238
16
239
16
23A
16
23B
16
23C
16
23D
16
23E
16
23F
16
220
16
221
16
222
16
223
16
224
16
225
16
226
16
227
16
228
16
229
16
22B
16
22C
16
22D
16
22E
16
22F
16
22A
16
Vertical position register 1
11
(VP1
11
)
Vertical position register 1
16
(VP1
16
)
Vertical position register 1
3
(VP1
3
)
Vertical position register 1
7
(VP1
7
)
Vertical position register 1
5
(VP1
5
)
Vertical position register 1
6
(VP1
6
)
Vertical position register 1
1
(VP1
1
)
Vertical position register 1
2
(VP1
2
)
Vertical position register 1
9
(VP1
9
)
Vertical position register 1
10
(VP1
10
)
b7
b0
b7
b0
Vertical position register 1
4
(VP1
4
)
Vertical position register 1
12
(VP1
12
)
?
?
?
?
VP1
1
1
Vertical position register 1
8
(VP1
8
)
Vertical position register 1
15
(VP1
15
)
Vertical position register 2
13
(VP2
13
)
Vertical position register 2
14
(VP2
14
)
Vertical position register 2
16
(VP2
16
)
Vertical position register 2
3
(VP2
3
)
Vertical position register 2
7
(VP2
7
)
Vertical position register 2
5
(VP2
5
)
Vertical position register 2
6
(VP2
6
)
Vertical position register 2
1
(VP2
1
)
Vertical position register 2
9
(VP2
9
)
Vertical position register 2
10
(VP2
10
)
Vertical position register 2
4
(VP2
4
)
Vertical position register 2
12
(VP2
12
)
Vertical position register 2
8
(VP2
8
)
Vertical position register 2
15
(VP2
15
)
Vertical position register 1
14
(VP1
14
)
Vertical position register 1
13
(VP1
13
)
Vertical position register 2
2
(VP2
2
)
Vertical position register 2
11
(VP2
11
)
VP1
1
2VP1
1
3VP1
1
4VP1
1
5VP1
1
6VP1
1
7VP1
1
8
VP1
2
1VP1
2
2VP1
2
3VP1
2
4VP1
2
5VP1
2
6VP1
2
7VP1
2
8
VP1
3
1VP1
3
2VP1
3
3VP1
3
4VP1
3
5VP1
3
6VP1
3
7VP1
3
8
VP1
4
1VP1
4
2VP1
4
3VP1
4
4VP1
4
5VP1
4
6VP1
4
7VP1
4
8
VP1
5
1VP1
5
2VP1
5
3VP1
5
4VP1
5
5VP1
5
6VP1
5
7VP1
5
8
VP1
6
1VP1
6
2VP1
6
3VP1
6
4VP1
6
5VP1
6
6VP1
6
7VP1
6
8
VP1
7
1VP1
7
2VP1
7
3VP1
7
4VP1
7
5VP1
7
6VP1
7
7VP1
7
8
VP1
8
1VP1
8
2VP1
8
3VP1
8
4VP1
8
5VP1
8
6VP1
8
7VP1
8
8
VP1
9
1VP1
9
2VP1
9
3VP1
9
4VP1
9
5VP1
9
6VP1
9
7VP1
9
8
VP1
10
1VP1
10
2VP1
10
3VP1
10
4VP1
10
5VP1
10
6VP1
10
7VP1
10
8
VP1
11
1VP1
11
2VP1
11
3VP1
11
4VP1
11
5VP1
11
6VP1
11
7VP1
11
8
VP1
12
1VP1
12
2VP1
12
3VP1
12
4VP1
12
5VP1
12
6VP1
12
7VP1
12
8
VP1
13
1VP1
13
2VP1
13
3VP1
13
4VP1
13
5VP1
13
6VP1
13
7VP1
13
8
VP1
14
1VP1
14
2VP1
14
3VP1
14
4VP1
14
5VP1
14
6VP1
14
7VP1
14
8
VP1
15
1VP1
15
2VP1
15
3VP1
15
4VP1
15
5VP1
15
6VP1
15
7VP1
15
8
VP1
16
1VP1
16
2VP1
16
3VP1
16
4VP1
16
5VP1
16
6VP1
16
7VP1
16
8
VP2
1
1VP2
1
2
VP2
2
1VP2
2
2
VP2
3
1VP2
3
2
VP2
4
1VP2
4
2
VP2
5
1VP2
5
2
VP2
6
1VP2
6
2
VP2
7
1VP2
7
2
VP2
8
1VP2
8
2
VP2
9
1VP2
9
2
VP2
10
1VP2
10
2
VP2
11
1VP2
11
2
VP2
12
1VP2
12
2
VP2
13
1VP2
13
2
VP2
14
1VP2
14
2
VP2
15
1VP2
15
2
VP2
16
1VP2
16
2
?
?
?
?
?
?
?
?
?
?
?
?
????????
????????
????????
????????
????????
????????
????????
????????
????????
????????
????????
????????
????????
????????
????????
????????
: Nothing is allocated
■SFR2 area (addresses 220
16
to 23F
16
)
Address Register
: undefined immediately after reset
?
Bit allocation State immediately after reset
(145 Seiten)
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