Renesas H8S/2655 Series Spezifikationen PDF herunterladen (Seite 15)

13

Improved read

access timing

In order to give external devices a

maximum of time to drive the required

data onto the bus,the read access edge

that latches the data,has been moved to

the end of the cycle. Therefore read

access time is improved by approximately

one quarter,compared with H8/300H.

Figures 10 & 11 illustrate this effect for

several frequencies.

Write data buffer

On H8S/26xx and on some H8S/23xx

derivatives,a write data buffer is

provided. This feature allows the CPU

to continue internal processing,while the

BSC takes care of slow write accesses

independently. Figure 12 shows an

example of the timing when the write

data buffer is used. When this function is

activated, if an external write or DMA

single address mode transfer continues for

2 states or longer,and there is an internal

access next,only an external write is

executed in the ﬁrst state. But from the

next state onward an internal access is

executed in parallel with the external

access,rather than waiting until it ends.

Bus release

On all H8S devices a mechanism is

provided to allow external bus masters to

obtain external bus ownership.

To request ownership an external master

must drive the BREQ pin low. After the

BREQ pins has been sampled low by the

H8S,the address bus,data bus and the

bus control pins are placed in a high

impedance state and the Bus

Acknowledge (BACK) signal is asserted

to signal to the external master that the

bus is now available. During bus release

state internal processing continues as long

as there is no external access.The

internal bus master, wishing to access the

external bus during bus release state,may

use the BREQO signal to indicate to the

external master that the bus ownership

should be given back. The external bus

master should respond by dropping

BREQ. BREQO can also be used to

signal that a refresh cycle for a DRAM is

pending.

100ns

50ns

Improved Access Time

10 12 16 20 MHz

H8S

H8/300H

200ns

T

1

Internal address bus

A

23

to A

0

External write cycle

HWR, LWR

T

2

T

W

T

W

T

3

On-chip memory read Internal I/O register read

Internal read signal

CS

n

D

15

to D

0

External address

Internal memory

External

space

write

Internal I/O register address

Figure 11

Figure 12

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 51 52

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