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Renesas PROM Programming Adapter PCA7408 Bedienungsanleitung Seite 42

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Seitenansicht 41
M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00 Oct 01, 2002 page 42 of 110
REJ03B0134-0100Z
Fig. 8.6.12 Address Data Communication Format
SS
l
a
v
e
a
d
d
r
e
s
s
A
D
a
t
aAD
a
t
aA
/
A PR
/
W
7
b
i
t
s“
0
”1
t
o
8
b
i
t
s1 to 8 bits
SS
l
a
v
e
a
d
d
r
e
s
s
A
D
a
t
a AD
a
t
a AP
7
b
i
t
s“
1
”1
t
o
8
b
i
t
s1 to 8 bits
(
1
)
A
m
a
s
t
e
r
-
t
r
a
n
s
m
i
t
t
e
r
t
r
a
n
s
m
i
t
s
d
a
t
a
t
o
a
s
l
a
v
e
-
r
e
c
e
i
v
e
r
S
S
l
a
v
e
a
d
d
r
e
s
s
1
s
t
7
b
i
t
s
A
A
D
a
t
a
7
b
i
t
s“
0
”8
b
i
t
s1 to 8 bits
(2) A master-receiver receives data from a slave-transmitte
r
S
l
a
v
e
a
d
d
r
e
s
s
2
n
d
b
y
t
e
A
D
a
t
aA
/
A P
1
t
o
8
b
i
t
s
S
S
l
a
v
e
a
d
d
r
e
s
s
1
s
t
7
b
i
t
s
A
A
7
b
i
t
s“
0
”8
b
i
t
s7 bit
s
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
l
a
v
e
a
d
d
r
e
s
s
2
n
d
b
y
t
e
Data
1 to 8 bits
Sr
Slave address
1st 7 bits
A
Data
A
P
1
t
o
8
b
i
t
s“1”
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S:START conditionP : STOP condition
A:ACK bit R/W : Read/Write bit
Sr : Restart condition
From master to slave
From slave to master
R
/
W
R
/
W
R/W R/W
8.6.12 Precautions when using multi-master
I
2
C-BUS interface
(1) Read-modify-write instruction
Precautions for executing the read-modify-write instructions such as
SEB, and CLB, is for each register of the multi-master I
2
C-BUS inter-
face are described below.
•I
2
C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become an arbitrary value.
•I
2
C address register (S0D)
When the read-modify-write instruction is executed for this register
at detection of the STOP condition, data may become an arbitrary
______
value. It is because hardware changes the read/write bit (RBW) at
the timing.
•I
2
C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
•I
2
C control register (S1D)
When the read-modify-write instruction is executed for this register
at detection of the START condition or at completion the byte trans-
fer, data may become an arbitrary value. Because hardware changes
the bit counter (BC0–BC2) at the timing.
•I
2
C clock control register (S2)
The read-modify-write instruction can be executed for this register.
(2) START condition generation procedure us-
ing multi-master
➀ Procedure example (The necessary conditions for the procedure
are described in ➁ to ➄ below).
•
•
LDA — (Take out slave address value)
SEI (Interrupt disabled)
BBS 5,S1,BUSBUSY
(BB flag confirmation and branch process)
BUSFREE:
STA S0 (Write slave address value)
LDM #$F0, S1
(Trigger START condition generation)
CLI (Interrupt enabled)
•
•
BUSBUSY:
CLI (Interrupt enabled)
•
•
➁ Use “STA,” “STX” or “STY” of the zero page addressing instruc-
tion for writing the slave address value to the I
2
C data shift register.
➂ Use “LDM” instruction for setting trigger of START condition gen-
eration.
④ Write the slave address value of ➁ and set trigger of START con-
dition generation as in ➂ continuously as shown in the procedure
example.
➄ Disable interrupts during the following three process steps:
• BB flag confirmation
• Write of slave address value
• Trigger of START condition generation
When the condition of the BB flag is bus busy, enable interrupts
immediately.
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