Renesas PROM Programming Adapter PCA7408 Bedienungsanleitung PDF herunterladen (Seite 41)

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP

Rev.1.00 Oct 01, 2002 page 41 of 110

REJ03B0134-0100Z

8.6.10 Example of Master Transmission

An example of master transmission in the standard clock mode, at

the SCL frequency of 100 kHz with the ACK return mode enable, is

shown below.

➀ Set a slave address in the high-order 7 bits of the I

C address

16) and “0” in the RBW bit.

➁ Set the ACK return mode and SCL = 100 kHz by setting “85

16” in

the I

C clock control register (address 00DB16).

➂ Set “1016” in the I

C status register (address 00D916) and hold the

SCL at HIGH.

④ Set a communication enable status by setting “4816” in the I

control register (address 00DA16).

➄ Set the address data of the destination of transmission in the high-

order 7 bits of the I

C data shift register (address 00D716) and set

“0” in the least significant bit.

⑥ Set “F016” in the I

C status register (address 00D916) to generate

a START condition. At this time, an SCL for 1 byte and an ACK

clock automatically occurs.

⑦ Set transmit data in the I

C data shift register (address 00D716). At

this time, an SCL and an ACK clock automatically occurs.

➇ When transmitting control data of more than 1 byte, repeat step ➆.

➈ Set “D016” in the I

C status register (address 00D916). After this, if

ACK is not returned or transmission ends, a STOP condition will

be generated.

8.6.11 Example of Slave Reception

An example of slave reception in the high-speed clock mode, at the

SCL frequency of 400 kHz, with the ACK non-return mode enabled

while using the addressing format, is shown below.

➀ Set a slave address in the high-order 7 bits of the I

C address

➁ Set the ACK non-return mode and SCL = 400 kHz by setting “2516”

in the I

C clock control register (address 00DB16).

➂ Set “1016” in the I

C status register (address 00D916) and hold the

SCL at HIGH.

④ Set a communication enable status by setting “4816” in the I

control register (address 00DA16).

➄ When a START condition is received, an address comparison is

executed.

⑥ •When all transmitted address are“0” (general call):

AD0 of the I

C status register (address 00D916) is set to “1” and

an interrupt request signal occurs.

•When the transmitted addresses match the address set in ➀:

ASS of the I

C status register (address 00D916) is set to “1” and

an interrupt request signal occurs.

•In the cases other than the above:

AD0 and AAS of the I

C status register (address 00D916) are set

to “0” and no interrupt request signal occurs.

⑦ Set dummy data in the I

C data shift register (address 00D716).

➇ When receiving control data of more than 1 byte, repeat step ➆.

➈ When a STOP condition is detected, the communication ends.

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