Renesas Single-Chip Microcomputer M34519T-MCU Spezifikationen PDF herunterladen (Seite 20)

High-performance CPU: 98 MIPS @ 48 MHz

USB 2.0 compliant

Built-in USB 2.0 function (full-speed) and USB 2.0 host (full-

speed)* controller

* V850ES/JG3-U and V850ES/JH3-U only

Extensive peripheral features

Backward-compatible with V850ES/Jx3.

Additional motor control capability and real-time counter

available.

Many USB-compliant features supported

Products are USB certied

Overview

Overview of USB speciﬁcations USB driver

None

PPON (USB power supply output) pin

OCI (overcurrent detection input) pin

USB host features

External clock input (f

USB

) = 48 MHzExternal

Internal

USB 2.0 (full speed)USB standard

External 6 MHz clock × Internal clock multiplied by 8 = 48 MHzUSB clock

1 ch

USB function

NoneControl, Bulk, Interrupt,

Isochronous

USB host transfer mode

None

V850ES/Jx3-H

DMA request (UDMARQn), DMA acknowledge (UDMAAKn) (n = 0, 1)

External USB DMA capability

Control × 2 (64 bytes), Bulk × 4 (64 bytes × 2),

Interrupt × 1 (8 bytes)

1 ch

V850ES/Jx3-U

USB function endpoint

conguration

USB host (OHCI)

* Assuming connection of µPD720150.

Features

Generic Name

All Flash 32-bit USB MCU (V850ES/Jx3-H, V850ES/Jx3-U)

USB function driver

Sample code supplied by Renesas Electronics free of charge.

Driver software provided by a partner company*.

USB host driver

Driver software provided by a partner company*.

* Partner companies: Tepco Uquest, Ltd., Grape Systems Inc.,

Ubiquitous Corporation

User application

Hardware

File system

OS dependent

USB host driver conguration

USB host driver

(OHCI, device, bus, etc.)

Class driver

: Supplied by partner company

USB function driver conguration

USB function driver

: Supplied by partner company

and Renesas Electronics

OS dependent

User application

Class driver

Hardware

MSC

Class driver

(option)

Class driver

(option)

MSC CDC

Other

or or

Two types: one for USB host and one for USB function

Provides development environment enabling system-level USB evaluation

Starter kit

Debug I/F, 7-seg LED, DIP switchLCD with touch panel function, Ethernet,

IrDA, audio I/O, external memory (SRAM),

RS-232C, expansion connectors, debug I/F

Main features included

TK-850/JG3HTK-850/JH3U-SP

Part number

256 KB ash memory, 32 KB + 8 KB RAM,

USB 2.0 function

512 KB ash memory, 48 KB + 8 KB RAM,

USB 2.0 function, USB 2.0 host

Main device features

µPD70F3760 (V850ES/JG3-H)

For USB Function

µPD70F3769 (V850ES/JH3-U)

For USB Host

Device mounted in

Item

USB Type

Starter kit for USB host

Starter kit for USB function

TK-850/JH3U-SP

TESSERA Technology Inc.

TK-850/JG3H

TESSERA Technology Inc.

* 1. Four channels in the V850ES/JC3-H and V850ES/JE3-H.

* 2. One channel in the V850ES/JC3-H and V850ES/JE3-H.

* 3. Not included in the V850ES/JC3-H.

* 4. Not included in the V850ES/JC3-H and V850ES/JE3-H.

* 5. µPD70F3819 (V850ES/JC3-H), 70F3825 (V850ES/JE3-H),

70F3770 (V850ES/JG3-H), and 70F3771 (V850ES/JH3-H) only

* 6. Not included in the 40-pin WQFN package.

Package

40-pin WQFN (6 × 6 mm, 0.5 mm pitch)

48-pin LQFP (7 × 7 mm, 0.5 mm pitch)

48-pin WQFN (7 × 7 mm, 0.5 mm pitch)

64-pin LQFP (10 × 10 mm, 0.5 mm pitch)

64-pin FBGA (6 × 6 mm, 0.65 mm pitch)

64-pin WQFN (9 × 9 mm, 0.5 mm pitch)

100-pin LQFP (14 × 14 mm, 0.5 mm pitch)

128-pin LQFP (14 × 20 mm, 0.5 mm pitch)

V850ES core

48 MHz (max.)

2.85 V to 3.6 V (single power supply)

Internal memory

Timer/counter

16-bit multifunction timer TAA × 6 ch*

16-bit multifunction timer TAB × 2 ch*

Motor control option (TMQOP) × 1 ch*

16-bit encode timer (TMT) × 1 ch

16-bit interval timer (TMM) × 4 ch

Other features

Low-voltage detector (LVI)

CRC circuit

Key interrupt

Clock monitor

Real-time output

5 V tolerant I/O

On-chip debugger

Watchdog timer

Real-time counter

A/D converter

10 bits × 12 ch*

Serial interface

CSI × 2 ch*

UART/CSI × 2 ch

UART/I

C × 1 ch*

UART/CSI/I

C × 1 ch

UART/I

C/CAN*

× 1 ch*

D/A converter

8 bits × 2 ch*

Memory controller (SRAM)

128-pin LQFP

Multiplexed/separate bus: address = 24 bits,

data = 8/16 bits, CS: 3 ch

100-pin LQFP

Multiplexed bus: address = 16 bits,

data = 8/16 bits, CS: 3 ch

DMA controller

4 ch, transfer unit: 8/16 bits

On-chip oscillator

(220 kHz)

Subclock oscillator

(32.768 kHz)

USB controller

USB 2.0 function (full-speed) × 1 ch

USB 2.0 host function (full-speed)

× 1 ch

Flash memor y 512 KB/RAM 48 KB + 8 KB*

Flash memor y 384 KB/RAM 40 KB + 8 KB*

Flash memor y 256 KB/RAM 32 KB + 8 KB*

Flash memor y 256 KB/RAM 24 KB

Flash memor y 128 KB/RAM 24 KB

Flash memor y 64 KB/RAM 24 KB

Flash memor y 32 KB/RAM 16 KB

Flash memor y 16 KB/RAM 8 KB

* 7. V850ES/JG3-U and V850ES/JH3-U only

* 8. Five channels in the 40-pin version of the V850ES/JC3-H,

six channels in the 48-pin version of the V850ES/JC3-H, and

ten channels in the V850ES/JE3-H.

* 9. Not included in the 40-pin WQFN package.

One channel in the 48-pin and 64-pin package.

*10. Data-only RAM

All Flash 32-bit Ethernet Controller MCU (V850ES/Jx3-E)

Package

JE3-E: 64-pin LQFP (10 × 10 mm, 0.5 mm pitch)

64-pin WQFN (9 × 9 mm, 0.5 mm pitch)

JF3-E: 80-pin LQFP (12 × 12 mm, 0.5 mm pitch)

JG3-E: 100-pin LQFP (14 × 14 mm, 0.5 mm pitch)

113-pin FBGA (8 × 8 mm, 0.65 mm pitch)

JH3-E: 128-pin LQFP (14 × 20 mm, 0.5 mm pitch)

JJ3-E: 144-pin LQFP ( 20 × 20 mm, 0.5 mm pitch)

V850ES core

50 MHz (max.)

2.85 to 3.6 V (single power supply)

Internal memory

Flash memory 512 KB/RAM 60 KB + 64 KB

Flash memory 512 KB/RAM 60 KB + 16 KB*

Flash memory 384 KB/RAM 60 KB + 64 KB*

Flash memory 384 KB/RAM 60 KB + 16 KB*

Flash memory 256 KB/RAM 60 KB + 16 KB*

Flash memory 256 KB/RAM 48 KB + 16 KB*

Flash memory 128 KB/RAM 32 KB + 16 KB*

Flash memory 64 KB/RAM 16KB + 16 KB*

Timers/counters

16-bit multifunction timer TAA × 6 ch

16-bit multifunction timer TAB × 2 ch

Motor control option (TABOP) × 1 ch

16-bit encode timer (TMT) × 1 ch

16-bit interval timer (TMM) × 4 ch

Other features

Low voltage detector

CRC circuit

Key interrupt

Clock monitor

Real-time output

(Not included in the JE3-E and JF3-E.)

5 V tolerant I/O

On-chip debugger

Watchdog timer

Real-time counter

Ethernet controller

10/100 Mbps Ethernet MAC × 1 ch

Serial interfaces

Except JJ3-E: UART (LIN)/CSI × 1 ch

JJ3-E: UART (LIN)/CSI × 3 ch

UART (LIN)/CSI (FIFO) × 1 ch

UART (FIFO)/CSI × 2 ch*

4, 5

UART (LIN)/CSI/I

C × 2 ch*

UART (LIN)/CSI (FIFO)

C x 1 ch

CSI (FIFO)*

× 1 ch*

JE3-E: CSI × 1 ch

JF3-E, JG3-E: CSI × 2 ch

C × 1 ch*

UART (LIN)/I

C/CAN*

× 1 ch

Memory controller (SRAM)

JH3-E: Multiplexed/separate address bus: 22 bits

Data bus: 8/16 bits

CS: 3 ch

JJ3-E: Multiplexed/separate address bus: 24 bits

Data bus: 8/16 bits

CS: 2 ch

DMA controller

4 ch, transfer unit: 8/16 bits

Internal oscillator

(220 kHz)

Subclock oscillator

(32.768 kHz)

A/D converter

JE3-E, JF3-E: 10 bits × 8 ch

JG3-E, JH3-E: 10 bits × 10 ch

JJ3-E: 10 bits × 12 ch

USB controller

USB 2.0 peripheral (full-speed) × 1 ch

* 1. Four channels in other than the V850ES/JH3-E and V850ES/JJ3-E.

* 2. One channel in other than the V850ES/JH3-E and V850ES/JJ3-E.

* 3. Not included in the V850ES/JE3-E.

* 4. V850ES/JH3-E and V850ES/JJ3-E only

* 5. One channel is assigned to two different pins.

* 6. One channel in the V850ES/JE3-E.

* 7. The same channel is assigned to two different pins.

* 8. V850ES/JJ3-E only

* 9. µPD70F3829 (V850ES/JE3-E), 70F3833 (V850ES/JF3-E),

70F3837 (V850ES/JG3-E), 70F3783 (V850ES/JH3-E), and

70F3786 (V850ES/JJ3-E) only

*10. Data-only RAM

High-performance CPU of 103 MIPS @ 50 MHz

Internal ash memory of up to 512 KB and RAM of up to 124 KB

On-chip Ethernet controller

On-chip 10/100 Mbps MAC eliminates the need to attach an

external Ethernet controller

Control your networks and systems using only the internal memory

Block diagram

Evaluation kit that can be used for evaluation and development at the system level

Network software in the form of a TCP/IP protocol stack

Renesas Electronics provides a free TCP/IP protocol stack -- the Compact TCP/IP Library*.

TCP/IP protocol stacks are also available from our partner companies.

* Also includes web server and mail client software.

Evaluation kit

TCP/IP protocol stacks provided by partner companies

TK-850/JH3E+NET

(V850ES/JH3-E mounted)

Made by TESSERA Technology Inc.

Qlism

USNetPlus

KASAGO

Cente

Ubiquitous TCP/IP

NEC Communication Systems

Nissin Systems Co., Ltd.

Zuken Elmic, Inc.

Data Technology Inc.

Ubiquitous Corporation

TCP/IP protocol stackPartner

Enhanced development environment and network software

MAC

- Enables IEEE802.3-compliant 10/100 Mbps

full-duplex and half-duplex communication as

well as ow control.

Uses MII as the physical layer device (PHY) interface

- Includes an on-chip VLAN detector

FIFO size: Transmission = 2 KB

Reception = 2 KB

Dedicated Ethernet controller DMAC

On-chip reception checksum calculator

compliant with RFC1071

On-chip Ethernet controller lets you build a low-cost system

MII I/O

buffer

TPO+

TPO-

TPI+

TPI-

PHY

MAC

FIFO

controller

Transmission

FIFO (2 KB)

Reception

FIFO (2 KB)

Reception

checksum

unit

Dedicated

Ethernet

controller

DMAC

Internal bus

38 39

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 50 51

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