Renesas Emulation Pod M306H2T-RPD-E Technical Information Seite 45

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M306H5T3-RPD-E User’s Manual 4. Specifications
REJ10J0866-0100Z Rev.1.00 Dec.16, 2004
Page 43 of 66
Vcc=5V
4.2 Operation Timing in Memory Expansion and Microprocessor Modes
4.2.1 Separate Bus Timing
Table 4.2 and Figure 4.1 show the bus timing in memory expansion and microprocessor modes (3-wait, accessing external
area).
Table 4.2 Memory expansion and microprocessor modes (3-wait, accessing external area)
Actual MCU
[ns]
This product [ns]
Symbol Item
Min. Max. Min. Max.
td(BCLK-AD) Address output delay time 40 See left
th(BCLK-AD) Address output hold time (BCLK standard) 4 See left
th(RD-AD) Address output hold time (RD standard) 0 -1
th(WR-AD) Address output hold time (WR standard) (*2) See left
td(BCLK-CS) Chip-select output delay time 40 See left
th(BCLK-CS) Chip-select output hold time (BCLK standard) 4 See left
td(BCLK-ALE) ALE signal output delay time 40 See left
th(BCLK-ALE) ALE signal output hold time -4 See left
td(BCLK-RD) RD signal output delay time 40 See left
th(BCLK-RD) RD signal output hold time 0 See left
td(BCLK-WR) WR signal output delay time 40 See left
th(BCLK-WR) WR signal output hold time 0 See left
td(BCLK-DB) Data output delay time (BCLK standard) 40 See left
th(BCLK-DB) Data output hold time (BCLK standard) 4 See left
td(DB-WR) Data output delay time (WR standard) (*1) See left
th(WR-DB) Data output hold time (WR standard) (*2) See left
*1 Calculated by the following formula according to the frequency of BCLK.
()
40
)(
100.5
9
×
BCLKf
n
n: "3" for 3-wait
*2 Calculated by the following formula according to the frequency of BCLK.
10
×
)(
100.5
9
BCLKf
[ns]
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