Renesas PCA7401 Technical Information PDF herunterladen (Seite 39)

MITSUBISHI MICROCOMPUTERS

M37270MF-XXXSP

M37270EF-XXXSP, M37270EFSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

Function

In conformity with Philips I

C-BUS

standard:

10-bit addressing format

7-bit addressing format

High-speed clock mode

Standard clock mode

In conformity with Philips I

C-BUS

standard:

Master transmission

Master reception

Slave transmission

Slave reception

16.1 kHz to 400 kHz (at φ

= 4 MHz)

Table 6. Multi-master I

C-BUS interface functions

Item

Format

Communication mode

SCL clock frequency

: System clock = f(XIN)/2

Note: We are not responsible for any third party’s infringement of

patent rights or other rights attributable to the use of the con-

trol function (bits 6 and 7 of the I

C control register at address

00F9

16) for connections between the I

C-BUS interface and

ports (SCL1, SCL2, SDA1, SDA2).

MULTI-MASTER I

C-BUS INTERFACE

The multi-master I

C-BUS interface is a circuit for serial communica-

tions conformed with the Philips I

C-BUS data transfer format. This

interface, having an arbitration lost detection function and a synchro-

nous function, is useful for serial communications of the multi-mas-

ter.

Figure 36 shows a block diagram of the multi-master I

C-BUS inter-

face and Table 6 shows multi-master I

C-BUS interface functions.

This multi-master I

C-BUS interface consists of the I

C address reg-

ister, the I

C data shift register, the I

C clock control register, the I

control register, the I

C status register and other control circuits.

Fig. 36. Block diagram of multi-master I

C-BUS interface

I C address register

b7 b0

SAD6 SAD5 SAD4 SAD3 SAD2 SAD1SAD0 RBW

Noise

elimination

circuit

Serial

data

(SDA)

Address comparator

I C data shift register

Data

control

circuit

I C clock control register

System clock ( φ )

Interrupt

generating

circuit

Interrupt

request signal

(IICIRQ)

MST TRX BB PIN

AL AAS AD0 LRB

I C status

b7 b0

BSEL1 BSEL0

10BIT

SAD

ALS

BC2 BC1 BC0

S1D I C clock control register

Bit counter

circuit

Clock

control

circuit

Noise

elimination

circuit

Serial

clock

(SCL)

b7 b0

ACK

BIT

FAST

MODE

CCR4 CCR3 CCR2 CCR1 CCR0

Internal data bus

Clock division

S0D

circuit

ES0

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 96 97

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