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4.2 Access Status

Table 4.2 lists the parameters for bus status (bus) that can be specified with HDI command line

interface or displayed as trace results.

Table 4.2 Bus Status Parameters

HDI Parameter

(Trace Display) Bus Status Description

DMAC

(DMAC)

On-chip DMAC Access by the MCU's DMAC

CACHE

(Cache)

Cache fill MCU internal cache fill cycle

DATA

(Data)

CPU data access Data access for instruction execution by

the CPU

PROG

(Prog)

CPU instruction fetch Instruction fetch access by the CPU

SLEEP_DMAC

(Sleep: DMAC)

Sleep status DMAC cycle was generated in sleep

mode.

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Renesas SH7050 Series Technical Information Seite 25