Renesas M3A-HS85 Technical Information PDF herunterladen (Seite 10)

SH7285 Group

Example of Initialization

REJ06B0860-0100/Rev.1.00 June 2009 Page 8 of 21

2.4 Setting in the Sample Program

Table 2 lists the setting in the sample program. Table 3 and

Table 4 list register settings for each module.

Table 2 Module Setting in the Sample Program

Module Setting

Clock pulse generator (CPG)

• Clock frequency (input clock is 12.5 MHz)

Internal clock: 100 MHz

Bus clock: 50 MHz

Peripheral clock: 50 MHz

MTU2S clock: 50 MHz

AD clock: 50 MHz

• Modules cleared the module standby function

MTU2S, MTU2, POE2, IIC3, ADC0, ADC1, CMT, SCIF3, SCI0,

SCI1, SCI2, SCI4, SSU, USB

Table 3 CPG Register Settings (1/2)

Frequency control register

(FRQCR)

H'FFFE 0010 H'0101

• STC[2:0] = "B'001":

Bus clock (Bφ) division ratio: 2

• IFC[2:0] = "B'000":

Internal clock (Iφ) division ratio: 1

• PFC[2:0] = "B'001":

Peripheral clock (Pφ) division ratio = 2

MTU2S clock frequency

control register (MCLKCR)

H'FFFE 0410 H'41

• MSDIVS[1:0] = "B'01":

MTU2S clock (Mφ) division ratio =2

AD clock frequency control

H'FFFE 0414 H'41

• ASDIVS[1:0] = "B'01":

AD clock (Aφ) division ratio = 2

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Renesas M3A-HS85 Technical Information Seite 10