
22
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
Timer A underflow
interrupt request
Timer A (high-order) (8)
Timer A (low-order) (8)
Timer A (high-order) latch (8)
Timer A (low-order) latch (8)
Timer A
operating
mode bits
Timer A write control bit
Data bus
X
IN
1/1
1/2
1/4
Timer A count
source selection bit
1/8
Output selection bit
P5
0
latch
TA
OUT
active
edge switch bit
P5
0
/TA
OUT
P5
0
direction
register
S
“0”
“1”
Q
Q
D
Compare register (high-order) (8)
Compare register (low-order) (8)
1/2
1/4
Divider
Noise filter sampling
clock selection bit
INT
0
0µs
Delay circuit
External trigger delay
time selection bit
4/f(X
IN
)
TA
OUT
output
control bit 1
TA
OUT
output
control bit 2
“0”
“1”
“0”
“1”
“10”
R
Timer A start
signal
INT
1
INT
2
“
00
”
“
01
”
“
10
”
“
11
”
Internal trigger start
“00”, “01”, “11”
“10”
Match
“00”, “01”, “11”
Timer A operating
mode bits
TA
OUT
active
edge switch bit
S
“0”
“1”
Q
Q
T
S
Pulse output mode
IGBT output mode
PWM mode
8/f(X
IN
)
16/f(X
IN
)
Note: The initial value of M version becomes “1” (output).
(Note)
Noise filter
(4-time same levels judgement)
Divider
Fig. 19 Block diagram of timer A
Fig. 20 Structure of timer A related registers
b7 b0
Timer A control register
(TACON : address 0031
16)
Noise filter sampling clock selection bit
0 : f(X
IN)/2
1 : f(X
IN)/4
External trigger delay time selection bits
0 0 : No delay
0 1 : ( 4/f(X
IN))µs
1 0 : ( 8/f(X
IN))µs
1 1 : (16/f(X
IN))µs
Timer A output control bit 1 (P5
6)
0 : Not used
1 : INT1 interrupt used
Timer A output control bit 2 (P5
7)
0 : Not used
1 : INT2 interrupt used
Not used (returns “0” when read)
b7 b0
Timer A mode register
(TAM : address 0030
16)
Timer A operating mode bits
00 : Timer mode
01 : Pulse output mode
10 : IGBT output mode
11 : PWM mode
Timer A write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch onl
y
Timer A count source selection bits
0 0 : f(X
IN)
0 1 : f(X
IN)/2
1 0 : f(X
IN)/4
1 1 : f(X
IN)/8
Timer A output active edge switch bit
0 : Output starts with “L” level
1 : Output starts with “H” level
Timer A count stop bit
0 : Count operating
1 : Count stop
Timer A output selection bit (P5
0)
0 : I/O port
1 : Timer A output
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