
Rev.1.00 2003.05.08
page 3 of 23
M65881AFP
BLOCK DIAGRAM
M
C
K
S
E
L
F
s
o
C
K
O
F
s
o
I
X
f
s
o
O
U
T
X
f
s
o
I
N
S
F
L
A
G
OUTR1
OUTL1
OUTR2
OUTL2
Sampling
Rate Converter
Gain Control
DATA
BCK
LRCK
S
C
D
T
S
C
S
H
I
F
T
S
C
L
A
T
C
H
18
17
16
2
41
39
4
I
N
I
T
N
S
P
M
U
T
E
X
f
s
i
I
N
Clock
Generator
( Primary )
Clock
Generator
( Secondary )
INIT/MUTE
Serial
Control
25
26
T
E
S
T
2
24
HPOUTR1
HPOUTL1
HPOUTR2
HPOUTL2
33
29
27
31
PWM
T
E
S
T
1
15
14
11 12 13
21
23
2210
6
36
∆Σ
S⇒P
-
M65881AFP
1
-
ABSOLUTE MAXIMUM RATINGS
4
-
ELECTRICAL CHARACTERISTICS
4
-
PIN DESCRIPTION
6
-
EXPLANATION OF OPERATION
7
-
1. DATA,BCK,LRCK
7
-
3. MCKSEL, XfsoIN, XfsoOUT
8
-
4. XfsiIN
8
-
2. SCDT, SCSHIFT, SCLATCH
8
-
PWM output control
10
-
7. OUTL1, OUTL2, OUTR1, OUTR2
10
-
9. NSPMUTE
11
-
10. INIT
11
-
11. TEST1, TEST2
11
-
12. Power supply and GND
11
-
13. Power sequences
12
-
SERIAL CONTROL
13
-
Rev.1.00 2003.05.08
14
-
2. System1 Mode
16
-
3. System2 Mode
18
-
Plastic 42pin 450mil SSOP
22
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