40
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Function
In conformity with Philips I
2
C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I
2
C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at φ= 4 MHz)
20.2 kHz to 312.5 kHz (at φ
= 5 MHz)
Table 9 Multi-master I
2
C-BUS interface functions
Item
Format
Communication mode
SCL clock frequency
System clock φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
MULTI-MASTER I
2
C-BUS INTERFACE
The multi-master I
2
C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I
2
C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchro-
nous functions, is useful for the multi-master serial
communications.
Figure 35 shows a block diagram of the multi-master I
2
C-BUS in-
terface and Table 9 lists the multi-master I
2
C-BUS interface
functions.
This multi-master I
2
C-BUS interface consists of the I
2
C address
register, the I
2
C data shift register, the I
2
C clock control register,
the I
2
C control register, the I
2
C status register, the I
2
C start/stop
condition control register and other control circuits.
When using the multi-master I
2
C-BUS interface, set 1 MHz or
more to φ.
Fig. 35 Block diagram of multi-master I
2
C-BUS interface
✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these components
an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
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