Renesas MN4 Spezifikationen Seite 1

APPLICATION NOTE R01AN0924EJ0100 Rev.1.00 Page 1 of 40 Feb 10, 2012 V850E2/MN4 CSIH Control Introduction This application note explains how t

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 10 of 40 Feb 10, 2012 4. Sample Application This section explains how to set up the CSIH

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 11 of 40 Feb 10, 2012 4.1.2 Master Direct-Access Transmit-Only Mode Master direct-acce

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 12 of 40 Feb 10, 2012 4.1.3 Slave Direct-Access Receive-Only Mode Slave direct-access

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 13 of 40 Feb 10, 2012 4.1.4 Master Dual-Buffer Transmit-Only Mode Master dual-buffer t

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 14 of 40 Feb 10, 2012 4.1.5 Slave Dual-Buffer Receive-Only Mode Slave dual-buffer recei

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 15 of 40 Feb 10, 2012 4.1.6 Communication Error Interrupt Processing If a communication

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 16 of 40 Feb 10, 2012 4.2 Register Setup This section explains how to set up the relevan

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 17 of 40 Feb 10, 2012 4.2.2 CSIH Control Register 2 (CSIHnCTL2) The CSIHnCTL2 register

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 18 of 40 Feb 10, 2012 Setting example CSIHnCTL2 = 0x2104; /* master mode;

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 19 of 40 Feb 10, 2012 4.2.3 CSIH Control Register 0 (CSIHnCTL0) The CSIHnCTL0 register

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 2 of 40 Feb 10, 2012 1. Overview This application note explains the following four opera

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 20 of 40 Feb 10, 2012 Figure 4.9 CSIHnCTL0 Register Format (2/2) CSIHnCTL0 = 0x00;

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 21 of 40 Feb 10, 2012 4.2.4 CSIH Control Register 1 (CSIHnCTL1) The CSIHnCTL1 register

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 22 of 40 Feb 10, 2012 Figure 4.11 CSIHnCTL1 Register Format (2/3)

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 23 of 40 Feb 10, 2012 Figure 4.12 CSIHnCTL1 Register Format (3/3) CSIHnCTL1 = 0x00010

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 24 of 40 Feb 10, 2012 4.2.5 CSIH Configuration Register x (CSIHnCFGx) The CSIHnCFGx reg

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 25 of 40 Feb 10, 2012 Figure 4.14 CSIHnCFGx Register Format (2/5)

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 26 of 40 Feb 10, 2012 Figure 4.15 CSIHnCFGx Register Format (3/5)

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 27 of 40 Feb 10, 2012 Figure 4.16 CSIHnCFGx Register Format (4/5)

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 28 of 40 Feb 10, 2012 Figure 4.17 CSIHnCFGx Register Format (5/5) CSIHnCFG0 = 0x0800

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 29 of 40 Feb 10, 2012 4.2.6 CSIH Memory Control Register 0 (CSIHnMCTL0) The CSIHnMCTL0

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 3 of 40 Feb 10, 2012 The main points in slave dual-buffer receive-only mode are illustra

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 30 of 40 Feb 10, 2012 4.2.7 CSIH Status Clear Register 0 (CSIHnSTCR0) The CSIH can dete

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 31 of 40 Feb 10, 2012 /* Clear status flags to 0 */ CSIHnTMOEC = 1; /* Clear timeout

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 32 of 40 Feb 10, 2012 4.3 Memory Modes The CSIH supports FIFO mode, dual buffer mode, tr

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 33 of 40 Feb 10, 2012 4.4 Function Specifications This section describes the specifica

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 34 of 40 Feb 10, 2012 [Function Name] hbus_initial() [Function] Initializes the AHB

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 35 of 40 Feb 10, 2012 [Function Name] display() [Function] Controls the LEDs accordi

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 36 of 40 Feb 10, 2012 [Function Name] csih_receive_2_initial() [Function] The CSIH3

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 37 of 40 Feb 10, 2012 [Function Name] csih_transmit_2_initial() [Function] The CSIH0

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 38 of 40 Feb 10, 2012 4.4.5 Interrupt Processing (interrupt.c) [Function Name] int_csi

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 39 of 40 Feb 10, 2012 [Function Name] int_csih3ire() [Function] Processes CSIH3 macr

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 4 of 40 Feb 10, 2012 The main points in master direct-access transmit-only mode (Job mod

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 40 of 40 Feb 10, 2012 Website and Support Renesas Electronics Website http://www.renesa

A-1 Revision Record Description Rev. Date Page Summary 1.00 Feb 10, 2012 — First edition issued

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed

Notice1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to chan

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 5 of 40 Feb 10, 2012 The main points in slave direct-access receive-only mode are illust

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 6 of 40 Feb 10, 2012 The basic communication specifications are shown below. Memory mode

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 7 of 40 Feb 10, 2012 1.4 Main Loop Processing • The operation of data transfer via the

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 8 of 40 Feb 10, 2012 2. Usage Environment This section provides the circuit diagram and

V850E2/MN4 CSIH Control R01AN0924EJ0100 Rev.1.00 Page 9 of 40 Feb 10, 2012 3. Software This section describes the organization of the compress