Renesas Single-Chip Microcomputer M37531T-ADS Technical Information PDF herunterladen (Seite 53)

MAEC TECHNICAL NEWS

No.M16C-71-0105

( 1 / 1)

GRADE

Setting procedure of processor mode bits

1. Precautions

Processor mode bits are allocated to bits 1 and 0 of the processor mode register 0. Regardless

of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,

never change the processor mode bits when changing the contents of other bits. Do not change

the processor mode bits simultaneously with other bits when changing the processor mode

bits “012” or “112”. Change the processor mode bits after changing the other bits.

Figure 1 shows the processor mode register 0 of M16C/62A group, and figure 2 shows the

setting procedure of processor mode bits.

Classification

Corrections and supplementary

explanation of document

✔ Notes

Knowhow

Others

Products Effected

M16C/80 Series

M16C/60 Series

Figure 1. Processor mode register 0

Figure 2. Setting procedure

Processor mode register 0 (Note 1)

Symbol Address When reset

PM0 0004

(Note 2)

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

0 0: Single-chip mode

0 1: Memory expansion mode

1 0: Do not set

1 1: Microprocessor mode

b1 b0

PM03

PM01

PM00

Processor mode bit

PM02

R/W mode select bit

0 : RD,BHE,WR

1 : RD,WRH,WRL

Software reset bit

The device is reset when this bit is set

to “1”. The value of this bit is “0” when

read.

PM04

0 0 : Multiplexed bus is not used

0 1 : Allocated to CS2 space

1 0 : Allocated to CS1 space

1 1 : Allocated to entire space (Note4)

b5 b4

Multiplexed bus space

select bit

PM05

PM06

PM07

Port P4

to P4

function

select bit (Note 3)

0 : Address output

1 : Port function

(Address is not output)

BCLK output disable bit

0 : BCLK is output

1 : BCLK is not output

(Pin is left floating)

Note 1: Set bit 1 of the protect register (address 000A

) to “1” when writing new

values to this register.

Note 2: If the V

voltage is applied to the CNV

, the value of this register when

reset is 03

. (PM00 and PM01 both are set to “1”.)

Note 3: Valid in microprocessor and memory expansion modes.

Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-

bit width.The processor operates using the separate bus after reset is revoked, so the entire

space multiplexed bus cannot be chosen in microprocessor mode.

to P3

become a port if the entire space multiplexed bus is chosen, so only 256 bytes can

be used in each chip select.

When changing into the following state after reset

• Memory expansion mode

• Entire space multiplexed bus

MOV.B #00110001B, PM0

MOV.B #00110000B, PM0 ; Setting other bits except the

; processor mode bits

MOV.B #00110001B, PM0

N.G. O.K.

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